參數(shù)資料
型號: MAX7032ATJ
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: 通信及網(wǎng)絡(luò)
英文描述: Low-Cost, Crystal-Based, Programmable, ASK/FSK Transceiver with Fractional-N PLL
中文描述: SPECIALTY TELECOM CIRCUIT, QCC32
封裝: 5 X 5 MM, TQFN-32
文件頁數(shù): 26/32頁
文件大?。?/td> 449K
代理商: MAX7032ATJ
M
Low-Cost, Crystal-Based, Programmable,
ASK/FSK Transceiver with Fractional-N PLL
26
______________________________________________________________________________________
CS
DIO
t
OFF
ASK_DATA OR
FSK_DATA
t
CPU
t
RF
t
ON
t
OFF
t
CPU
t
RF
t
ON
t
LOW
Figure 10. DRX Mode Sequence of the MAX7032
Set OFPS1 to be 1 and OFPS0 to be 1. That sets the
t
OFF
time base (1 LSB) to be 7680μs. Set REG 0x06
and REG 0x07 to be FFFF, which is 65535 in decimal.
Therefore, the total t
OFF
is:
t
OFF
= 7680μs x 65535 = 8min 23s
During t
OFF
, the MAX7032 is operating with very low
supply current (23.4μA typ), where all its modules are
turned off, except for the t
OFF
timer itself. Upon com-
pletion of the t
OFF
time, the MAX7032 signals the user
by asserting DIO low.
CPU Recovery Timer (t
CPU
)
The CPU recovery timer, t
CPU
(see Figure 10) is used
to delay power up of the MAX7032, thereby providing
extra power savings and giving the CPU time to com-
plete its own power-on sequence. The CPU is signaled
to begin powering up when the DIO line is pulled low
by the MAX7032 at the end of t
OFF
. Then, t
CPU
begins
counting, while DIO is held low by the MAX7032. At the
end of t
CPU
, the t
RF
counter begins.
t
CPU
is an 8-bit timer, configured through register 0x08.
The possible t
CPU
settings are summarized in Table 13.
The data written to the t
CPU
register (register 0x08) is
multiplied by 120μs to give the total t
CPU
time. See the
example below. On power-up, the CPU timer register is
reset to zero and must be written before using DRX
mode.
Set REG 0x08 to be FF in hex, which is 255 in decimal.
Therefore, the total t
CPU
is:
t
CPU
= 120μs x 255 = 30.6ms
RF Settling Timer (t
RF
)
The RF settling timer, t
RF
(see Figure 10), allows the RF
sections of the MAX7032 to power up and stabilize
before ASK or FSK data is received. t
RF
begins count-
ing once t
CPU
has expired. At the beginning of t
RF
, the
modules selected in the power control register (register
0x00) are all powered up and the peak detectors are in
the track mode and have the t
RF
period to settle.
t
RF
is a 16-bit timer, configured through register 0x09
(upper byte) and register 0x0A (lower byte). The possi-
ble t
RF
settings are listed in Table 14. The data written
to the t
RF
register (register 0x09 and register 0x0A) are
multiplied by 120μs to give the total t
RF
time. See the
example in the
CPU Recovery Time
(
t
CPU
)
section. On
power-up, the RF timer registers are reset to zero and
must be written before using DRX mode.
Table 13. CPU Recovery Timer (t
CPU
)
Configuration
TIME BASE
(μs)
MIN t
CPU
REG 0x08 = 0x01
(μs)
MAX t
CPU
REG 0x08 = 0xFF
(ms)
120
120
30.6
t
RF
TIME BASE
(μs)
MIN t
RF
REG 0x09 = 0x00
REG 0x0A = 0x01
(μs)
120
MAX t
RF
REG 0x09 = 0xFF
REG 0x0A = 0xFF
(s)
7.86
120
Table 14. RF Settling Timer (t
RF
)
Configuration
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