參數(shù)資料
型號: MAX7032ATJ
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: 通信及網(wǎng)絡(luò)
英文描述: Low-Cost, Crystal-Based, Programmable, ASK/FSK Transceiver with Fractional-N PLL
中文描述: SPECIALTY TELECOM CIRCUIT, QCC32
封裝: 5 X 5 MM, TQFN-32
文件頁數(shù): 15/32頁
文件大?。?/td> 449K
代理商: MAX7032ATJ
M
Low-Cost, Crystal-Based, Programmable,
ASK/FSK Transceiver with Fractional-N PLL
______________________________________________________________________________________
15
The configuration shown in Figure 2 can create a
Butterworth or Bessel response. The Butterworth filter
offers a very flat amplitude response in the passband
and a rolloff rate of 40dB/decade for the two-pole filter.
The Bessel filter has a linear phase response, which
works well for filtering digital data. To calculate the
value of the capacitors, use the following equations,
along with the coefficients in Table 1:
where f
C
is the desired 3dB corner frequency.
For example, choose a Butterworth filter response with
a corner frequency of 5kHz:
Choosing standard capacitor values changes C
F1
to
470pF and C
F2
to 220pF. In the
Typical Application Circuit
,
C
F1
and C
F2
are named C16 and C17, respectively.
Data Slicer
The data slicer takes the analog output of the data filter
and converts it to a digital signal. This is achieved by
using a comparator and comparing the analog input to
a threshold voltage. The threshold voltage is set by the
voltage on the DS- pin, which is connected to the nega-
tive input of the data-slicer comparator.
Numerous configurations can be used to generate the
data-slicer threshold. For example, the circuit in Figure
3 shows a simple method using only one resistor and
one capacitor. This configuration averages the analog
output of the filter and sets the threshold to approxi-
mately 50% of that amplitude. With this configuration,
the threshold automatically adjusts as the analog signal
varies, minimizing the possibility for errors in the digital
data. The values of R and C affect how fast the thresh-
old tracks the analog amplitude. Be sure to keep the
corner frequency of the RC circuit much lower (about
10 times) than the lowest expected data rate.
With this configuration, a long string of NRZ zeros or ones
can cause the threshold to drift. This configuration works
best if a coding scheme, such as Manchester coding,
which has an equal number of zeros and ones, is used.
Figure 4 shows a configuration that uses the positive and
negative peak detectors to generate the threshold. This
configuration sets the threshold to the midpoint between
a high output and a low output of the data filter.
Peak Detectors
The maximum peak detector (PDMAX) and minimum
peak detector (PDMIN), with resistors and capacitors
shown in Figure 4, create DC output voltages equal to
the high and low peak values of the filtered ASK or FSK
demodulated signals. The resistors provide a path for
the capacitors to discharge, allowing the peak detec-
tors to dynamically follow peak changes of the data fil-
ter output voltages.
C
k
1 414
)(3 14 5
kHz
pF
C
k
kHz
pF
F
F
1
2
1 000
.
1 414 100
)(3 14 5
450
(4 100
225
=
=
)(
)
.
)
C
b
a
k
f
C
a
k
f
F
F
1
2
100
(
4100
(
=
=
)( )( )
)( )( )
MAX7032
C
DS-
DS+
R
DATA
SLICER
DATA
Figure 3. Generating Data Slicer Threshold Using a Lowpass
Filter
MAX7032
RSSI OR
FSK DEMOD
100k
C
F2
C
F1
100k
DF
OP+
DS+
Figure 2. Sallen-Key Lowpass Data Filter
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