參數(shù)資料
型號: MAX7032ATJ
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: 通信及網(wǎng)絡
英文描述: Low-Cost, Crystal-Based, Programmable, ASK/FSK Transceiver with Fractional-N PLL
中文描述: SPECIALTY TELECOM CIRCUIT, QCC32
封裝: 5 X 5 MM, TQFN-32
文件頁數(shù): 12/32頁
文件大?。?/td> 449K
代理商: MAX7032ATJ
M
Low-Cost, Crystal-Based, Programmable,
ASK/FSK Transceiver with Fractional-N PLL
12
______________________________________________________________________________________
Pin Description
PIN
NAME
FUNCTION
1
PAV
DD
Power-Amplifier Supply Voltage. Bypass to GND with 0.01μF and 220pF capacitors placed as close
to the pin as possible.
2
ROUT
Envelope-Shaping Output. ROUT controls the power-amplifier envelope’s rise and fall times. Connect
ROUT to the PA pullup inductor or optional power-adjust resistor. Bypass the inductor to GND as
close to the inductor as possible with 680pF and 220pF capacitors as shown in the
Typical
Application Circuit
.
3
TX/RX1
Transmit/Receive Switch Throw. Drive T/
R
high to short TX/RX1 to TX/RX2. Drive T/
R
low to disconnect
TX/RX1 from TX/RX2. Functionally identical to TX/RX2.
4
TX/RX2
Transmit/Receive Switch Pole. Typically connected to ground. See the
Typical Application Circuit
.
5
PAOUT
Power-Amplifier Output. Requires a pullup inductor to the supply voltage (or ROUT if envelope
shaping is desired), which may be part of the output-matching network to an antenna.
6
AV
DD
Analog Power-Supply Voltage. AV
DD
is connected to an on-chip +3.0V regulator in 5V operation.
Bypass AV
DD
to GND with 0.1μF and 220pF capacitors placed as close to the pin as possible.
Low-Noise Amplifier Input. Must be AC-coupled.
7
LNAIN
8
LNASRC
Low-Noise Amplifier Source for External Inductive Degeneration. Connect an inductor to GND to set
the LNA input impedance.
9
LNAOUT
Low-Noise Amplifier Output. Must be tied to AV
DD
through a parallel LC tank filter. AC-couple to
MIXIN+.
10
11
12
13
14
15
16
17
18
19
20
21
MIXIN+
MIXIN-
MIXOUT
IFIN-
IFIN+
PDMIN
PDMAX
DS-
DS+
OP+
DF
RSSI
Noninverting Mixer Input. Must be AC-coupled to the LNA output.
Inverting Mixer Input. Bypass to AV
DD
with a capacitor as close to LNA LC tank filter as possible.
330
Mixer Output. Connect to the input of the 10.7MHz filter.
Inverting 330
IF Limiter Amplifier Input. Bypass to GND with a capacitor.
Noninverting 330
IF Limiter Amplifier Input. Connect to the output of the 10.7MHz IF filter.
Minimum-Level Peak Detector for Demodulator Output
Maximum-Level Peak Detector for Demodulator Output
Inverting Data Slicer Input
Noninverting Data Slicer Input
Noninverting Op Amp Input for the Sallen-Key Data Filter
Data Filter Feedback Node. Input for the feedback of the Sallen-Key data filter.
Buffered Received-Signal-Strength Indicator Output
22
T/
R
Transmit/
Receive
. Drive high to put the device in transmit mode. Drive low or leave unconnected to
put the device in receive mode. It is internally pulled down. This function is also controlled by a
configuration register.
23
ENABLE
Enable. Drive high for normal operation. Drive low or leave unconnected to put the device into
shutdown mode.
24
25
DATA
CLKOUT
Receiver Data Output/Transmitter Data Input
Divided Crystal Clock Buffered Output
26
DV
DD
Digital Power-Supply Voltage. Bypass to GND with 0.01μF and 220pF capacitors placed as close to
the pin as possible.
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