參數(shù)資料
型號: MAX7032
廠商: Maxim Integrated Products, Inc.
英文描述: Low-Cost, Crystal-Based, Programmable, ASK/FSK Transceiver with Fractional-N PLL
中文描述: 低成本、基于晶振的可編程ASK/FSK收發(fā)器,帶有N分頻PLL
文件頁數(shù): 24/32頁
文件大小: 449K
代理商: MAX7032
Oscillator Frequency Register (Address 0x05)
The MAX7032 has an internal frequency divider that
divides down the crystal frequency to 100kHz. The
MAX7032 uses the 100kHz clock signal when calibrat-
ing itself and also to set image-rejection frequency. The
hexadecimal value written to the oscillator frequency
register is the nearest integer result of f
XTAL
/ 100kHz.
For example, if data is being received at 315MHz, the
crystal frequency is 12.67917MHz. Dividing the crystal
frequency by 100kHz and rounding to the nearest inte-
ger gives 127, or 0x7F hex. So for 315MHz, 0x7F would
be written to the oscillator frequency register.
AGC Dwell Timer (Address 0x03)
The AGC dwell timer holds the AGC in low-gain state
for a set amount of time after the power level drops
below the AGC switching threshold. After that set
amount of time, if the power level is still below the AGC
threshold, the LNA goes into high-gain state. This is
important for ASK since the modulated data may have
a high level above the threshold and a low level below
the threshold, which without the dwell timer would
cause the AGC to switch on every bit.
M
Low-Cost, Crystal-Based, Programmable,
ASK/FSK Transceiver with Fractional-N PLL
24
______________________________________________________________________________________
CKOUT
CDIV1
CDIV0
CLOCKOUT
FREQUENCY
0
1
1
1
1
X
0
0
1
1
X
0
1
0
1
Disabled at logic 0
f
XTAL
f
XTAL
/ 2
f
XTAL
/ 4
f
XTAL
/ 8
Table 10. Clock Output Divider Ratio
Configuration
BIT ID
BIT NAME
BIT LOCATION
(0 = LSB)
FUNCTION
LCKD
Lock detect
7
1 = Internal PLL is locked
0 = Internal PLL is not locked so the
MAX7032 does not receive or transmit data
GAINS
AGC gain state
6
1 = LNA in high-gain state
0 = LNA in low-gain state
CLKON
Clock/crystal alive
5
1 = Valid clock at crystal inputs
0 = No valid clock signal seen at the crystal
inputs
X
X
X
None
None
None
4
3
2
Zero
Zero
Zero
PCALD
Polling timer calibration
done
1
1 = Polling timer calibration is completed
0 = Polling timer calibration is in progress or
not completed
FCALD
FSK calibration done
0
1 = FSK calibration is completed
0 = FSK calibration is in progress or not
completed
Table 9. Status Register (Read Only) (Address: 0x1A)
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