參數(shù)資料
型號： MAX7032
廠商： Maxim Integrated Products, Inc.
英文描述： Low-Cost, Crystal-Based, Programmable, ASK/FSK Transceiver with Fractional-N PLL
中文描述： 低成本、基于晶振的可編程ASK/FSK收發(fā)器，帶有N分頻PLL
文件頁數(shù)： 19/32頁
文件大小： 449K
代理商： MAX7032
M
Low-Cost, Crystal-Based, Programmable,
ASK/FSK Transceiver with Fractional-N PLL
______________________________________________________________________________________
19
REGISTER A[5:0]
REGISTER NAME
DESCRIPTION
0x00
Power configuration
Enables/disables the LNA, AGC, mixer, baseband, peak
detectors, PA, and RSSI output (see Table 5).
0x01
Control
Controls AGC lock, gain state, peak-detector tracking, polling
timer and FSK calibration, clock signal output, and sleep mode
(see Table 6).
0x02
Configuration0
Sets options for modulation, TX/RX mode, manual-gain mode,
discontinuous receive mode, off-timer and on-timer prescalers
(see Table 7).
0x03
Configuration1
Sets options for automatic FSK calibration, clock output, output
clock divider ratio, AGC dwell timer (see Tables 8, 10, 11, and 12).
0x05
Oscillator frequency
Sets the internal clock frequency divisor. This register must be set
to the integer result of f
XTAL
/ 100kHz (see the
Oscillator
Frequency Register
section).
0x06
0x07
Off timer—t
OFF
(upper byte)
Off timer—t
OFF
(lower byte)
Sets the duration that the MAX7032 remains in low-power mode
when DRX is active (see Table 12).
0x08
CPU recovery timer—t
CPU
Increases maximum time the MAX7032 stays in lower power mode
while CPU wakes up when DRX is active (see Table 13).
0x09
RF settling timer—t
RF
(upper
byte)
0x0A
RF settling timer—t
RF
(lower
byte)
During the time set by the RF settling timer, the MAX7032 is
powered on with the peak detectors and the data outputs disabled
to allow time for the RF section to settle. DIO must be driven low at
any time during t
LOW
= t
CPU
+ t
RF
+ t
ON
or the timer sequence
restarts (see Table 14).
0x0B
0x0C
On timer—t
ON
(upper byte)
On timer—t
ON
(lower byte)
Transmitter low-frequency
setting—TxLOW (upper byte)
Sets the duration that the MAX7032 remains in active mode when
DRX is active (see Table 15).
0x0D
0x0E
Transmitter low-frequency
setting—TxLOW (lower byte)
Sets the low frequency (FSK) of the transmitter or the carrier
frequency of ASK for the fractional-N synthesizer.
0x0F
Transmitter high-frequency
setting—TxHIGH (upper byte)
0x10
Transmitter high-frequency
setting—TxHIGH (lower byte)
Sets the high frequency (FSK) of the transmitter for the fractional-N
synthesizer.
0x1A
Status register (read only)
Provides status for PLL lock, AGC state, crystal operation, polling
timer, and FSK calibration (see Table 9).
Table 3. Register Summary
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MAX7032ATJ+ 功能描述:射頻收發(fā)器 Crystal-Based Prog ASK/FSK Transceiver RoHS:否 制造商:Atmel 頻率范圍:2322 MHz to 2527 MHz 最大數(shù)據(jù)速率:2000 Kbps 調(diào)制格式:OQPSK 輸出功率:4 dBm 類型: 工作電源電壓:1.8 V to 3.6 V 最大工作溫度:+ 85 C 接口類型:SPI 封裝 / 箱體:QFN-32 封裝:Tray
MAX7032ATJ+T 功能描述:射頻收發(fā)器 Crystal-Based Prog ASK/FSK Transceiver RoHS:否 制造商:Atmel 頻率范圍:2322 MHz to 2527 MHz 最大數(shù)據(jù)速率:2000 Kbps 調(diào)制格式:OQPSK 輸出功率:4 dBm 類型: 工作電源電壓:1.8 V to 3.6 V 最大工作溫度:+ 85 C 接口類型:SPI 封裝 / 箱體:QFN-32 封裝:Tray
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