參數(shù)資料
型號: MAX5851ETL+T
廠商: Maxim Integrated Products
文件頁數(shù): 9/18頁
文件大?。?/td> 0K
描述: IC DAC 8BIT DUAL 80MSPS 40-TQFN
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 2,500
設(shè)置時間: 12ns
位數(shù): 8
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 2
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 40-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 40-TQFN-EP(6x6)
包裝: 帶卷 (TR)
輸出數(shù)目和類型: 4 電流,單極
采樣率(每秒): 80M
MAX5851
Dual, 8-Bit, 80Msps, Current-Output DAC
______________________________________________________________________________________
17
Intermodulation Distortion (IMD)
The two-tone IMD is the ratio expressed in dBc of either out-
put tone to the worst 3rd-order (or higher) IMD products.
Static Performance Parameter Definitions
Integral Nonlinearity (INL)
Integral nonlinearity (INL) is the deviation of the values
on an actual transfer function from a line drawn
between the end points of the transfer function, once
offset and gain errors have been nullified. For a DAC,
the deviations are measured at every individual step.
Differential Nonlinearity (DNL)
Differential nonlinearity (DNL) is the difference between
an actual step height and the ideal value of 1 LSB. A
DNL error specification no more negative than -1 LSB
guarantees monotonic transfer function.
Offset Error
Offset error is the current flowing from positive DAC
output when the digital input code is set to zero. Offset
error is expressed in LSBs.
Gain Error
A gain error is the difference between the ideal and the
actual full-scale output current on the transfer curve,
after nullifying the offset error. This error alters the slope
of the transfer function and corresponds to the same
percentage error in each step. The ideal current is
defined by reference voltage at 32 x VREFO / RSET.
Settling Time
The settling time is the amount of time required from the
start of a transition until the DAC output settles to its
new output value to within the converter’s specified
accuracy.
Glitch Impulse
A glitch is generated when a DAC switches between
two codes. The largest glitch is usually generated
around the midscale transition, when the input pattern
transitions from 011…111 to 100…000. This occurs due
to timing variations between the bits. The glitch impulse
is found by integrating the voltage of the glitch at the
midscale transition over time. The glitch impulse is usu-
ally specified in pV-s.
Chip Information
TRANSISTOR COUNT: 9035
PROCESS: CMOS
Table 4. Part Selection Table
PART
SPEED (Msps)
RESOLUTION
MAX5851
80
8 bit, dual
MAX5852
165
8 bit, dual
MAX5853
80
10 bit, dual
MAX5854
165
10 bit, dual
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