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參數(shù)資料
| 型號(hào)： | MAX5851ETL+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 2/18頁 |
| 文件大小： | 0K |
| 描述： | IC DAC 8BIT DUAL 80MSPS 40-TQFN |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 設(shè)置時(shí)間： | 12ns |
| 位數(shù)： | 8 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 40-WFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 40-TQFN-EP（6x6） |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 4 電流，單極 |
| 采樣率（每秒）： | 80M |
MAX5851
Dual, 8-Bit, 80Msps, Current-Output DAC
10
______________________________________________________________________________________
Pin Description
PIN
NAME
FUNCTION
1
DA7/PD
Channel A Input Data Bit 7 (MSB)/Power-Down
2
DA6/DACEN Channel A Input Data Bit 6/DAC Enable Control
3
DA5/IDE
Channel A Input Data Bit 5/Interleaved Data Enable
4
DA4/REN
Channel A Input Data Bit 4/Reference Enable. Setting REN = 0 enables the internal reference. Setting
REN = 1 disables the internal reference.
5
DA3/G3
Channel A Input Data Bit 3/Channel A Gain Adjustment Bit 3
6
DA2/G2
Channel A Input Data Bit 2/Channel A Gain Adjustment Bit 2
7
DA1/G1
Channel A Input Data Bit 1/Channel A Gain Adjustment Bit 1
8
DA0/G0
Channel A Input Data Bit 0 (LSB)/Channel A Gain Adjustment Bit 0
9, 10,
21, 22
N.C.
No Connection. Do not connect to these pins.
11
DB7
Channel B Input Data Bit 7 (MSB)
12
DB6
Channel B Input Data Bit 6
13
DB5
Channel B Input Data Bit 5
14
DB4
Channel B Input Data Bit 4
15
DB3
Channel B Input Data Bit 3
16
DVDD
Digital Power Input. See the Power Supplies, Bypassing, Decoupling, and Layout section for more details.
17
DGND
Digital Ground
18
DB2
Channel B Input Data Bit 2
19
DB1
Channel B Input Data Bit 1
20
DB0
Channel B Input Data Bit 0 (LSB)
23
CW
Active-Low Control Word Write Pulse. The control word is latched on the rising edge of CW.
24
DCE
Active-Low Differential Clock Enable Input. Drive DCE low to enable differential clock inputs
CLKXP and CLKXN. Drive DCE high to disable the differential clock inputs and enable the single-
ended CLK input.
25
CLKXP
Positive Differential Clock Input. With DCE = 0, CLKXP and CLKXN are enabled. With DCE = 1, CLKXP
and CLKXN are disabled. Connect CLKXP to CGND when the differential clock is disabled.
26
CLKXN
Negative Differential Clock Input. With DCE = 0, CLKXP and CLKXN are enabled. With DCE = 1, CLKXP
and CLKXN are disabled. Connect CLKXN to CVDD when the differential clock is disabled.
27, 30
CVDD
Clock Power Input. See the Power Supplies, Bypassing, Decoupling, and Layout section for more details.
28
CLK
Single-Ended Clock Input/Output. With the differential clock disabled (DCE = 1), CLK becomes a
single-ended conversion clock input. With the differential clock enabled (DCE = 0), CLK is a single-
ended output that mirrors differential clock inputs CLKXP and CLKXN. See the Clock Modes section for
more information on CLK.
29
CGND
Clock Ground
31
REFO
Reference Input/Output. REFO serves as a reference input when the internal reference is disabled. If the
internal 1.24V reference is enabled, REFO serves as an output for the internal reference. When the
internal reference is enabled, bypass REFO to AGND with a 0.1F capacitor.
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