參數(shù)資料
型號(hào)： MAX5725AAUP+T
廠商： Maxim Integrated Products
文件頁(yè)數(shù)： 34/35頁(yè)
文件大小： 0K
描述： IC DAC 12BIT SRL 20TSSOP
標(biāo)準(zhǔn)包裝： 2,500
設(shè)置時(shí)間： 4.5µs
位數(shù)： 12
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
電壓電源： 模擬和數(shù)字
功率耗散（最大）： 1.08W
工作溫度： -40°C ~ 125°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 20-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 20-TSSOP
包裝： 帶卷 (TR)
輸出數(shù)目和類(lèi)型： 8 電流，單極
MAX5723/MAX5724/MAX5725
Ultra-Small, Octal-Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference and SPI Interface
8
Maxim Integrated
Note 3: Electrical specifications are production tested at TA = +25°C. Specifications over the entire operating temperature range
are guaranteed by design and characterization. Typical specifications are at TA = +25°C.
Note 4: DC performance is tested without load, VREF = VDD.
Note 5: Linearity is tested with unloaded outputs to within 20mV of GND and VDD.
Note 6: Gain and offset calculated from measurements made with VREF = VDD at codes 30 and 4065 for MAX5725, codes 8 and
1016 for MAX5724, and codes 2 and 254 for MAX5723.
Note 7: Subject to zero- and full-scale error limits and VREF settings.
Note 8: Measured with all other DAC outputs at midscale with one channel transitioning 0 to full scale.
Note 9: On power-up, the device initiates an internal 200s (typ) calibration sequence. All commands issued during this time will
be ignored.
Note 10: Guaranteed by design.
Note 11: All channels active at VFS, unloaded. Static logic inputs with VIL = VGND and VIH = VDDIO for all inputs.
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 2.7V to 5.5V, VDDIO = 1.8V to 5.5V, VGND = 0V, CL = 200pF, RL = 2kI, TA = -40NC to +125NC, unless otherwise noted.)
(Note 3)
Figure 1. SPI Serial Interface Timing Diagram
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SCLK Fall to DOUT Hold
tDOH
DPHA = 0, CLOAD = 0pF
2
ns
SCLK Rise to DOUT Hold
tDOH
DPHA = 1, CLOAD = 0pF
2
ns
CSB Fall to DOUT Fall
tDOE
Enable time, CLOAD = 20pF
20
ns
CSB Rise to DOUT Hi-Z
tDOZ
Disable time
2
.7V < VDDIO < 5.5V
20
ns
1.8V < VDDIO < 2.7V
40
DIN23
12
DIN
SCLK
CSB
DOUT
(DPHA = 1)
DOUT
(DPHA = 0)
tDS
tDH
tCL
tCSA
tCSH1
tDOZ
tDOH
tCSF
Z
tCH
tCSH0
Z
tCSPW
tDOE
tCLPW
tCSC
tCSS0
tSCLK
34
56
78
91023241
DIN22 DIN21 DIN20 DIN19 DIN18 DIN17 DIN16 DIN15 DIN14
DO15
DO1
DO0
DIN1
DIN0
DIN23’
DO15
DO14
DO1
DO0
tLDH
tLDPW
tDOT
tDOH
CLR
LDAC
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