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參數(shù)資料
| 型號(hào)： | MAX5550ETE+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 15/15頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 10BIT DUAL 30MA 16-TQFN |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 設(shè)置時(shí)間： | 30µs |
| 位數(shù)： | 10 |
| 數(shù)據(jù)接口： | I²C，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-WFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 16-TQFN（3x3） |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 2 電流，單極 |
| 采樣率（每秒）： | 10M |
I2C Compatibility (SPI/
I2C = GND)
The MAX5550 is compatible with existing I2C systems
(Figure 2). SCL and SDA are high-impedance inputs;
SDA has an open-drain output that pulls the data line
low during the ninth clock pulse. SDA and SCL require
pullup resistors (2.4k
or greater) to VDD. Optional
resistors (24
) in series with SDA and SCL protect the
device inputs from high-voltage spikes on the bus lines.
Series resistors also minimize crosstalk and undershoot
of the bus signals. The communication protocol sup-
ports standard I2C 8-bit communications. The device’s
address is compatible with 7-bit I2C addressing proto-
col only. Ten-bit address formats are not supported.
Only write commands are accepted by the MAX5550.
Note: I2C readback is not supported.
Bit Transfer
One data bit transfers during each SCL rising edge.
The MAX5550 requires nine clock cycles to transfer
data into or out of the DAC register. The data on SDA
must remain stable during the high period of the SCL
clock pulse. Changes in SDA while SCL is high are
read as control signals (see the START and STOP
Conditions section). Both SDA and SCL idle high.
START and STOP Conditions
The master initiates a transmission with a START condi-
tion (S), (a high-to-low transition on SDA with SCL high).
The master terminates a transmission with a STOP con-
dition (P), (a low-to-high transition on SDA while SCL is
high) (Figure 3). A START condition from the master
signals the beginning of a transmission to the
MAX5550. The master terminates transmission by issu-
ing a STOP condition. The STOP condition frees the
bus. If a repeated START condition (Sr) is generated
instead of a STOP condition, the bus remains active.
MAX5550
Dual, 10-Bit, Programmable, 30mA
High-Output-Current DAC
_______________________________________________________________________________________
9
+1.25V
REFERENCE
IFSADJ
RFSADJ
FSADJ_
OUT_
VDD
GND
CURRENT-SOURCE
ARRAY DAC
Figure 1. Reference Architecture and Output Current Adjustment
*Negative output current values = 0
FULL-SCALE OUTPUT CURRENT (mA)*
RFSADJ (k
)
1mA–2mA
1.5mA–3mA
2.5mA–5mA
4.5mA–9mA
8mA–16mA
15mA–30mA
Calculated
1% EIA Std
1.00
1.500
2.500
4.500
8.00
15.00
40
40.2
1.25
1.875
3.125
5.625
10.00
18.75
35
34.8
1.50
2.250
3.750
6.750
12.00
22.50
30
30.1
1.75
2.625
4.375
7.875
14.00
26.25
25
24.9
2.00
3.000
5.000
9.000
16.00
30.00
20
20.0
Table 1. Full-Scale Output Current and RFSADJ_ Selection Based on a +1.25V (typ)
Reference Voltage
*See the command summary in Table 4.
DAC CODE
IOUT_
11 1111 1111
10 0000 0000
00 0000 0001*
00 0000 0000
0
Table 2. DAC Output Code Table
1023
1024
×
I
FS
OS
||
512
1024
×
I
FS
OS
||
1024
I
FS
OS
||
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