參數(shù)資料
型號(hào)： MAX5550ETE+T
廠商： Maxim Integrated Products
文件頁(yè)數(shù)： 10/15頁(yè)
文件大?。?/td> 0K
描述： IC DAC 10BIT DUAL 30MA 16-TQFN
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 2,500
設(shè)置時(shí)間： 30µs
位數(shù)： 10
數(shù)據(jù)接口： I²C，串行，SPI?
轉(zhuǎn)換器數(shù)目： 2
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 16-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 16-TQFN（3x3）
包裝： 帶卷 (TR)
輸出數(shù)目和類型： 2 電流，單極
采樣率（每秒）： 10M
MAX5550
Dual, 10-Bit, Programmable, 30mA
High-Output-Current DAC
4
_______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +2.7V to +5.25V, GND = 0, VREFIN = +1.25V, internal reference, RFSADJ_ = 20k
; compliance voltage = (VDD - 0.6V),
VSCLK/SCL = 0, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VDD = +3.0V and TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Bus Free Time Between a STOP
and START Condition
tBUF
1.3
s
Setup Time for STOP Condition
tSU:STO
160
ns
Maximum Capacitive Load for
Each Bus Line
CB
400
pF
SPI TIMING CHARACTERISTICS (Figure 6)
SCLK Clock Period
tCP
100
ns
SCLK Pulse-Width High
tCH
40
ns
SCLK Pulse-Width Low
tCL
40
ns
CS Fall to SCLK Rise Setup Time
tCSS
25
ns
SCLK Rise to
CS Rise Hold Time
tCSH
50
ns
DIN Setup Time
tDS
40
ns
DIN Hold Time
tDH
0ns
SCLK Fall to DOUT Transition
tDO1
CLOAD = 30pF
40
ns
CS Fall to DOUT Enable
tCSE
CLOAD = 30pF
40
ns
CS Rise to DOUT Disable
tCSD
CLOAD = 30pF
40
ns
SCLK Rise to
CS Fall Delay
tCS0
50
ns
CS Rise to SCLK Rise Hold Time
tCS1
40
ns
CS Pulse-Width High
tCSW
100
ns
SPI TIMING CHARACTERISTICS FOR DAISY CHAINING (Figure 6)
SCLK Clock Period
tCP
200
ns
SCLK Pulse-Width High
tCH
80
ns
SCLK Pulse-Width Low
tCL
80
ns
CS Fall to SCLK Rise Setup Time
tCSS
25
ns
SCLK Rise to
CS Rise Hold Time
tCSH
50
ns
DIN Setup Time
tDS
40
ns
DIN Hold Time
tDH
0ns
SCLK Fall to DOUT Transition
tDO1
CLOAD = 30pF
40
ns
CS Fall to DOUT Enable
tCSE
CLOAD = 30pF
40
ns
CS Rise to DOUT Disable
tCSD
CLOAD = 30pF
40
ns
SCLK Rise to
CS Fall Delay
tCS0
50
ns
CS Rise to SCLK Rise Hold Time
tCS1
40
ns
CS Pulse-Width High
tCSW
100
ns
Note 1: 100% production tested at TA = +25°C. Limits over temperature are guaranteed by design.
Note 2: INL linearity is guaranteed from code 60 to code 1024.
Note 3: Connect a resistor from FSADJ_ to GND to adjust the full-scale current. See the Reference Architecture and Operation section.
Note 4: Settling time is measured from (0.25 x full scale) to (0.75 x full scale).
Note 5: The device draws higher supply current when the digital inputs are driven with voltages between (VDD - 0.5V) and (GND +
0.5V). See the Supply Current vs. Digital Input Voltage graph in the Typical Operating Characteristics.
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