參數(shù)資料
型號(hào)： MAX4455ECQ
廠商： MAXIM INTEGRATED PRODUCTS INC
元件分類： 畫面疊加
英文描述： Triple Differential Transceivers 20-SOIC -40 to 85
中文描述： ON-SCREEN DISPLAY IC, PQFP100
封裝： 14 X 14 MM, 1 MM HEIGHT, TQFP-100
文件頁數(shù)： 9/30頁
文件大?。?/td> 663K
代理商： MAX4455ECQ
M
Arbitrary Graphics On-Screen Display
Video Generator
_______________________________________________________________________________________
9
Connect V
K1
to the MAX4356/MAX4358 V
DD
logic sup-
ply, or a 5V logic supply for TTL output compatibility.
OSDFILL_ Reference Voltage (RSET)
Set the video DAC
’
s full-scale output current for all
eight channels by connecting a resistor between RSET
and ground. The nominal 11.75k
R
RSET
provides a
100 IRE video output level when OSDFILL_ outputs are
terminated with 75
resistors to ground. R
RSET
can typ-
ically range between 5k
and 15k
.
The full-scale OSD DAC output current = (106.5) / R
RSET
.
The full-scale OSD DAC output voltage is the OSD DAC
output current
×
R
OSDFILL
, where ROSDFILL_ is the termi-
nation resistor to AGND at OSDFILL_.
Crystal Oscillator
The MAX4455 requires a 40.5MHz clock. Connect a 3.3V
crystal oscillator module to XTAL1/SYNC and leave
XTAL2 unconnected, or connect a lower cost 40.5MHz
fundamental mode crystal between XTAL1/SYNC and
XTAL2. The MAX4455 is designed to operate with a 50%
clock duty cycle, but typically operates with up to 40% to
60% duty cycles. The oscillator circuitry typically requires
10ms to settle after the DV
DD
supply is powered up.
Microprocessor Interface
The MAX4455 μP interface includes a byte-wide
address/data bus (AD7
–
AD0) for parallel programming
of the MAX4455, write strobe input (
WR
), read strobe
input (
RD
), active-high chip-select input (CS), address
or data-select input (ADDR/
DATA
), and a ready/busy
hand-shaking output (RDY/
BSY
) (Figures 5 and 6). The
MAX4455 allows for interfacing to a μP powered from a
different supply than the MAX4455 by connecting V
H1
to the μP supply. For example, the MAX4455 can be
operated with a single 3.3V supply, while the μP inter-
face can be operated with 3.3V or 5V logic levels by
connecting V
H1
to the μP power supply.
Host Access Protocol Sequence
1) Host sets ADD/
DATA
= 1.
2) Host outputs register address on AD7
–
AD0.
3) Host pulses
WR
low, then high to write register
address.
4) Host checks RDY/
BSY
= 1 (host waits if RDY/
BSY
= 0).
For register data writes:
1) Host sets ADD/
DATA
= 0.
2) Host drives register data on AD7
–
AD0.
3) Host pulses
WR
low, then high.
For register data reads:
1) Host removes drive from AD7
–
AD0 in anticipation of
register read operation and sets ADD/
DATA
= 0.
2) Host then pulses
RD
low and reads register data.
3) The MAX4455 three states when
RD
is deasserted
(high).
SDRAM Memory Interface
The MAX4455 interfaces directly to a 16Mb SDRAM
with 16-bit-wide data bus. The MAX4455 performs all
SDRAM support functions, including refresh, RAS/CAS
timing, data addressing, and CPU access cycles for
host processor read/write support.
MAX4455 Register Description
OSD Register Organization
The host processor controls each of the MAX4455
’
s
eight video channels through eight groups (blocks) of 8-
bit command, status, data, and address registers, plus
one multichannel register block. The register set descrip-
tion for a single channel is described in Table 2. The
eight identical sets of 16 registers (14, plus 2 reserved)
are selected by 4 LSB bits in the host interface address
field as described in Tables 3 and 4. The lower address
bits select which register is accessed within any given
channel. Even channels can share buffer data for display
PIXEL DATA
GRAY SCALE
DESCRIPTION
0000
0
Transparent
—
no OSD
insertion. Background
video appears normally.
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
7 IRE (black)
13 IRE
20 IRE
27 IRE
33 IRE
40 IRE
47 IRE
53 IRE
60 IRE
67 IRE
73 IRE
80 IRE
87 IRE
93 IRE
100 IRE (white)
Table 1. Pixel Data Mapping (4 Bits per
Pixel)
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