參數(shù)資料
型號: MAX4455ECQ
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: 畫面疊加
英文描述: Triple Differential Transceivers 20-SOIC -40 to 85
中文描述: ON-SCREEN DISPLAY IC, PQFP100
封裝: 14 X 14 MM, 1 MM HEIGHT, TQFP-100
文件頁數(shù): 10/30頁
文件大?。?/td> 663K
代理商: MAX4455ECQ
M
Arbitrary Graphics On-Screen Display
Video Generator
10
______________________________________________________________________________________
among even channels. Odd channels can also share
buffer data for display among odd channels (see the
Memory Sharing
section).
Detailed Description of the Channel-N
Block Registers
QPH, QPL (Quad Pixel Register)
Read/write pixel data 16-bits at a time to the quad pixel
registers due to the SDRAM memory organization. The 4
MSBs (nybble) of QPH represent the left-most pixel and
the 4 LSBs of QPL represent the right-most pixel (4 bits
per pixel). To transfer the QPH/QPL value into display
memory, set the QPHORIZ/QPLINE registers and then
write 0000 0010 to the command register (see
Command
Register
section).
QPHORIZ
This 8-bit value is the address of the quad pixel within
the line specified by QPLINE HI and QPLINE LO. A
zero in QPHORIZ addresses the leftmost displayed
quad pixel in the specified line, and increasing
QPHORIZ addresses indexes towards the right-hand
side of the video screen. Valid values range from zero
to 177. Write a 1 in the HINC bit of the channel status
register to enable autoincrement of QPHORIZ.
QPHORIZ autoincrement saturates at 177.
QPLINEH, QPLINEL
The QPLINE_ 9-bit address specifies the horizontal line
of the quad pixel to be accessed (host read or write).
The 9th bit resides in the LSB position (bit 0) of the
QPLINEH register. The lower 8 bits of the 9-bit address
are specified by QPLINEL. Table 5 shows valid dis-
played line numbers. Note that for NTSC, lines 1
through 20 are never valid, as this is the vertical blank
interval. Write a 1 in the VINC bit of the channel status
register to enable autoincrement of QPLINE_. QPLINE_
autoincrement saturates at 511.
VERTICAL 1 (20 NTSC LINES, 25 PAL LINES)
VERTICAL 2 (21 NTSC LINES, 26 PAL LINES)
H
H
5
712T NTSC,
702T PAL
APPROX
144T NTSC,
162T PAL
HBLANK PIXEL COUNT IS DEPENDENT
UPON INCOMING VIDEO HLINE PERIOD
F
3
F
3
FIELD 1 ACTIVE VIDEO (242H NTSC, 287H PAL)
FIELD 2 ACTIVE VIDEO (242H NTSC, 287 PAL)
t
= 33.367ms
T = 1 / (13.5MHz) = 74.074ns = 1 PIXEL TIME
1ST DISPLAYED PIXEL POSITION IS CONTROLLED
BY HOFFSET REGISTER
Figure 4. OSD Raster Dimensions
MAX4455
μ
P DIGITAL SUPPLY
2.7V TO 5.5V
DATA BUS
WR
RD
ADD/DATA
μ
P HOST INTERFACE
μ
P
AD7
AD0
RDY/BSY
CS
GPIO
8
V
CC
V
H1
DV
DD
MAX4455 DIGITAL SUPPLY
3V TO 3.6V
Figure 5. μP Host Interface
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