參數(shù)資料
型號: MAX4455ECQ
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: 畫面疊加
英文描述: Triple Differential Transceivers 20-SOIC -40 to 85
中文描述: ON-SCREEN DISPLAY IC, PQFP100
封裝: 14 X 14 MM, 1 MM HEIGHT, TQFP-100
文件頁數(shù): 4/30頁
文件大小: 663K
代理商: MAX4455ECQ
M
Arbitrary Graphics On-Screen Display
Video Generator
4
_______________________________________________________________________________________
MEMORY INTERFACE TIMING CHARACTERISTICS
(DV
DD
= 3.0V to 3.6V, AV
DD
= 2.7V to 5.5V, V
K1
= V
H1
= 2.7V to 5.5V, AGND = DGND = 0, R
RSET
= 11.75k
±1%, R
OSDFILL_
= 75
,
f
XTAL1/SYNC
= 40.5MHz, T
A
= -40
°
C to +85
°
C, unless otherwise noted. Typical values are at T
A
= +25
°
C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Digital Output Maximum Rise
Time
Digital Output Maximum Fall Time
t
CLCH
15pF load (Note 5)
3
ns
t
CHCL
15pF load (Note 5)
3
ns
Maximum Digital Out to Digital
Out Skew
t
SKEW
15pF load, except D0
D15
±2.5
ns
Note 1:
f
XTAL1/SYNC
is production tested at 1MHz. Application operating frequency is f
XTAL1/SYNC
= 40.5MHz.
Note 2:
Pertains to host interface pins: ADDR/
DATA
, CS,
WR
,
RD
, AD7
AD0, RDY/
BSY
. V
H1
is connected to μP host power supply
rail (2.7V to 5.5V).
Note 3:
Read operation is combinational. Access time is from the latter of either
RD
or CS.
Note 4:
Pertains to XTAL1/SYNCIN and XTAL2 pins (external clock is supplied to XTAL1/SYNCIN pin). All input signals are specified
with t
R
= t
F
= 5ns (10% to 90% of DV
DD
), and timed from a voltage level of 1.6V.
Note 5:
Specified using 10% and 90% points.
t
CHCX
V
IH
V
IH
t
CLCX
t
CHCL
t
CLCH
XTAL1/SYNC
MEMORY
LOGIC I/O
V
IL
V
IL
AD7
AD0
WR
ADD/DATA
AD7
AD0
RD
ADD/DATA
HOST ADDRESS OR DATA WRITE OPERATION
HOST DATA READ OPERATION
t
1
t
2
t
3
t
4
t
5
CS
CS
ADDR/DATA IN
READ DATA OUT
Figure 2. Clock and Memory Timing Diagram
Figure 1. μP Host Interface Timing
Timing Diagrams
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