
M
Arbitrary Graphics On-Screen Display
Video Generator
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15
LOSALL
This register is common to all eight channels and
reflects the status of sync presence on each of the
eight VIDIN_ inputs. If valid composite sync is present
at each of the eight VIDIN_ inputs, this register contains
all zeros. If any channel loses sync for more than one
horizontal line period, a flag is set for that respective
channel indicating sync loss. Normally, the host
processor polls this register periodically and checks for
nonzero flag bits, indicating loss of video on any or all
channels. This feature detects vandalism, security
threats, or simple camera/link failure. The loss of sync
register is described below:
MWRITE
Multiple write command register. Trigger multiple write
operations to OSD frame buffer memory by writing to
MWRITE, specifying which channels should receive
data. This is useful in updating graphics common to
multiple channels (i.e., time of day, etc.). Writing a 1
triggers writes to the desired channel as defined below.
This register autoclears itself after a multiple write cycle
completes. The multiple write register is described
below:
Control
Control bits for the multichannel block register. VINC,
when set to 1, enables autoincrement of QPLINEH/L in
the multichannel block after each host multichannel
write to OSD memory. HINC, when set to 1, enables
autoincrement of QPHORIZ in the multichannel block
after each host multichannel write operation to OSD
buffer memory. The control register is described below:
BIT7
0
BIT0
0
0
0
VINC
HINC
0
0
BIT7
Ch7
BIT0
Ch0
Ch6
Ch5
Ch4
Ch3
Ch2
Ch1
BIT7
Ch7
BIT0
Ch0
Ch6
Ch5
Ch4
Ch3
Ch2
Ch1
Detailed Description of the Multichannel
Block Registers
QPH, QPL
Pixel data is read/written 16 bits at a time to the quad
pixel registers due to the SDRAM memory organization.
The most significant 4 bits (nybble) of QPH represents
the leftmost pixel and the least significant 4 bits of QPL
represents the rightmost pixel (4 bits per pixel). Table 1
shows pixel data mapping. QPH and QPL for the multi-
channel block is read/written the same as the individual
channel-N register function, except multichannel pixel
data is used for multiple write operations to selected
channels.
QPHORIZ
This 8-bit value is the address of the quad pixel within
the line specified by QPLINE HI and QPLINE LO. A
zero value in QPHORIZ addresses the leftmost dis-
played quad pixel in the specified line and increasing
QPHORIZ addresses indexes towards the right-hand
side of the video screen. This register addresses multi-
channel write operations. Valid values range from zero
to 177. Write a 1 in the HINC bit of the multichannel
CONTROL register to enable autoincrement of
QPHORIZ. QPHORIZ autoincrement saturates at 177.
QPLINEH, QPLINEL
This 9-bit address specifies the horizontal line of the
quad pixel to be accessed (host read or write). QPLINE
HI is only 1 bit that resides in the LSB (bit 0) of the
QPLINE HI register. The lower 8 bits of the 9-bit
address are specified by QPLINE LO. Valid displayed
line numbers range from 0 to 483 NTSC (511 PAL). This
register is used for addressing for multichannel write
operations. Write a 1 in the VINC bit of the channel
CONTROL register to enable autoincrement of
QPLINE_. QPLINE_ autoincrement saturates at 511.