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參數(shù)資料
| 型號： | MAX3676EHJ+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 5/15頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK RECOVERY 32-TQFP |
| 產(chǎn)品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 2,500 |
| 類型： | 時鐘和數(shù)據(jù)恢復（CDR），多路復用器 |
| PLL： | 是 |
| 主要目的： | SONET/SDH |
| 輸入： | PECL |
| 輸出： | PECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:2 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 622.08MHz |
| 電源電壓： | 3 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-TQFP |
| 供應商設備封裝： | 32-TQFP（5x5） |
| 包裝： | 帶卷 (TR) |
MAX3676
622Mbps, 3.3V Clock-Recovery and
Data-Retiming IC with Limiting Amplifier
______________________________________________________________________________________
13
allowable pattern-dependent jitter, peak-to-peak
(seconds); and BW = typical system bandwidth, nor-
mally 0.6 to 1.0 times the data rate (Hertz). If the PDJ is
still larger than desired, continue increasing the value of
CIN. Note that to maintain stability when using the
MAX3676 analog inputs (ADI+, ADI-), it is important to
keep the low-frequency cutoff associated with COLC
below the corner frequency associated with CIN (fC)
(Table 1).
PDJ can also be present due to insufficient high-fre-
quency bandwidth (Figure 10). If the amplifiers are not
fast enough to allow for complete transitions during sin-
gle-bit patterns, or if the amplifier does not allow ade-
quate settling time, high-frequency PDJ can result.
Pulse-Width Distortion
Finally, PWD occurs when the midpoint crossing of a
0–1 transition and a 1–0 transition does not occur at the
same level (Figure 11). DC offsets and nonsymmetrical
rising and falling edge speeds both contribute to PWD.
For a 1–0 bit stream, calculate PWD as follows:
PWD = [(width of wider pulse) -
(width of narrower pulse)]/2
Phase Adjust
The internal clock and data alignment in the MAX3676
is well maintained close to the center of the data eye.
Although not required, this sampling point can be shift-
ed using the PHADJ inputs to optimize BER perfor-
mance. The PHADJ inputs operate with differential
input signals to approximately ±1V. A simple resistor
divider with a bypass capacitor is sufficient to set up
these levels. When the PHADJ inputs are not used, they
should be tied directly to VCC.
Figure 10. Pattern-Dependent Jitter Due to High-Frequency
Rolloff
AMPLITUDE
TIME
MIDPOINT
LONG
CONSECUTIVE
BIT STREAM
0-1-0 BIT STREAM
HF PDJ
Figure 11. Pulse-Width Distortion
AMPLITUDE
TIME
MIDPOINT
WIDTH OF A ONE
WIDTH OF A ZERO
PWD RESULTS WHEN THE WIDTH
OF A ZERO DOES NOT EQUAL
THE WIDTH OF A ONE.
tFALL
≠ tRISE
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MAX3677CTJ+ | 制造商:Microsemi Corporation 功能描述:+3.3V, LOW-JITTER CLOCK GEN W/MULT OUT - Trays 制造商:Microsemi Corporation 功能描述:Microsemi MAX3677CTJ+ Clocks - Timers 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC CLOCK GENERATOR PROGR 32TQFN 制造商:Microsemi Corporation 功能描述:IC CLOCK GENERATOR PROGR 32TQFN |
| MAX3677CTJ+T | 制造商:Microsemi Corporation 功能描述:+3.3V, LOW-JITTER CLOCK GEN W/MULT OUT - Tape and Reel |
| MAX3677EVKIT+ | 制造商:Microsemi Corporation 功能描述:MAX3677 EVALUATION KIT - Boxed Product (Development Kits) 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:KIT EVALUATION MAX MAX3677 |
| MAX3678EVKIT+ | 功能描述:時鐘和定時器開發(fā)工具 Not Available From Mouser RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Modules 類型:Clock Conditioners 工具用于評估:LMK04100B 頻率:122.8 MHz 工作電源電壓:3.3 V |
| MAX3678UTN+ | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 Low-Jitter Frequency Synthesizer RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
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