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參數(shù)資料
| 型號： | MAX3676EHJ+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 12/15頁 |
| 文件大小： | 0K |
| 描述： | IC CLOCK RECOVERY 32-TQFP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 類型： | 時鐘和數(shù)據(jù)恢復(fù)（CDR），多路復(fù)用器 |
| PLL： | 是 |
| 主要目的： | SONET/SDH |
| 輸入： | PECL |
| 輸出： | PECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:2 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 622.08MHz |
| 電源電壓： | 3 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-TQFP |
| 供應(yīng)商設(shè)備封裝： | 32-TQFP（5x5） |
| 包裝： | 帶卷 (TR) |
MAX3676
622Mbps, 3.3V Clock-Recovery and
Data-Retiming IC with Limiting Amplifier
6
_______________________________________________________________________________________
Pin Description
32
CFILT
RSSI Filter Capacitor Input. Connect a 47nF capacitor between CFILT and VCC.
30
ADI+
Positive Analog Data Input, 622.08Mbps serial-data stream
29
ADI-
Negative Analog Data Input, 622.08Mbps serial-data stream
28
INSEL
Input Select. Connect to GND to select digital data inputs or VCC for analog data inputs.
27
DDI-
Negative Digital Data Input, PECL, 622.08Mbps serial-data stream
26
DDI+
Positive Digital Data Input, PECL, 622.08Mbps serial-data stream
23
FIL+
Positive Filter Input. PLL loop filter connection. Internally connected to VCC.
22
FIL-
Negative Filter Input. PLL loop filter connection. Connect a 2.2μF capacitor between FIL- and FIL+.
20
PHADJ+
Positive Phase-Adjust Input. Used to optimally align internal PLL phase. Attach to VCC if not used.
19
PHADJ-
Negative Phase-Adjust Input. Used to optimally align internal PLL phase. Attach to VCC if not used.
NAME
FUNCTION
1
OLC+
Positive Offset-Correction Loop Capacitor Input
2
OLC-
Negative Offset-Correction Loop Capacitor Input
PIN
3
RSSI
Received-Signal-Strength Indicator Output
4, 8, 16,
24, 25
GND
Supply Ground
9, 12, 15,
18, 21, 31
VCC
Positive Supply Voltage
7
LOP
Loss-of-Power Output, TTL. Limiting amplifier loss-of-power monitor. Asserts high when input signal
is below threshold set by VTH.
6
VTH
Voltage Threshold Input. Threshold voltage for loss-of-power monitor. Attach to VCC if LOP function
is not used.
5
INV
Op Amp Inverting Input. Attach to ground if op amp is not used.
17
LOL
Loss-of-Lock Output, TTL. PLL loss-of-lock monitor, active low (see the
Design Procedure section).
14
SDO+
Positive Serial-Data Output, PECL, 622.08Mbps
13
SDO-
Negative Serial-Data Output, PECL, 622.08Mbps
11
SCLKO+
Positive Serial-Clock Output, PECL, 622.08MHz. SDO+ is clocked out on the rising edge of SCLKO+.
10
SCLKO-
Negative Serial-Clock Output, PECL, 622.08MHz. SDO- is clocked out on the falling edge of SCLKO-.
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