- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄384665 > MAX3672 (Maxim Integrated Products, Inc.) Low-Jitter 155MHz/622MHz Clock Generator PDF資料下載
參數(shù)資料
| 型號： | MAX3672 |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | Low-Jitter 155MHz/622MHz Clock Generator |
| 中文描述： | 低抖動、155MHz/622MHz時鐘發(fā)生器 |
| 文件頁數(shù)： | 9/12頁 |
| 文件大?。?/td> | 493K |
| 代理商： | MAX3672 |
Setting the Higher-Order Poles
Spurious noise is generated by the phase detector
switching at the compare frequency, where f
COMPARE
= f
VCO
/(N
1
N
2
). Reduce the spurious noise from the
digital phase detector by placing a higher-order pole
(HOP) at a frequency much less than the compare fre-
quency. The HOP should, however, be placed high
enough in frequency that it does not decrease the over-
all loop-phase margin and impact jitter peaking. These
two conditions can be met by selecting the HOP fre-
quency to be (K
4) < f
HOP
< f
COMPARE
, where K is
the loop bandwidth.
The HOP can be implemented either by providing a
compensation capacitor C
2
, which produces a pole at:
or by adding a lowpass filter, consisting of R
3
and C
3
,
directly on the VCO tuning port, which produces a pole at:
Using R
3
and C
3
might be preferable for filtering more
noise in the PLL, but it might still be necessary to provide
filtering through C
2
when using large values of R
1
and N
1
2
, to prevent clipping in the op amp.
Setting the Optional Output
The MAX3672 optional clock output can be set to binary
subdivisions of the main clock frequency. The PSEL1
and PSEL2 pins control the binary divisions. Table 5
shows the pin configuration and possible divider ratios.
Applications Information
PECL Interfacing
The MAX3672 outputs (MOUT+, MOUT-, POUT+,
POUT-) are designed to interface with PECL signal levels
and should be biased appropriately. Proper termination
requires an external circuit that provides a Thevenin
equivalent of 50
to VCC - 2.0V and controlled-imped-
ance transmission lines. To ensure best performance,
the differential outputs must have balanced loads. If the
optional clock output is not used, the output can be left
floating to save power.
Layout
The MAX3672 performance can be significantly affected
by circuit board layout and design. Use good high-
frequency design techniques, including minimizing
ground inductance and using fixed-impedance trans-
mission lines on the reference and VCO clock signals.
Power-supply decoupling should be placed as close to
the die as possible. Take care to isolate the input from
the output signals to reduce feedthrough.
VCO Selection
The MAX3672 is designed to accommodate a wide
range of VCO gains, positive or negative transfer
slopes, and V
CC
-referenced or ground-referenced con-
trol voltages. These features allow the user a wide
range of options in VCO selection; however, the proper
VCO must be selected to allow the clock generator cir-
cuitry to operate at the optimum levels. When selecting
f
R C
π
HOP
=
1
2
3
f
k
C
HOP
(
)(
)
=
1
2 20
2
M
Low-Jitter 155MHz/622MHz Clock Generator
_______________________________________________________________________________________
9
INPUT PIN NSEL1 INPUT PIN NSEL2
V
CC
OPEN
GND
V
CC
OPEN
GND
V
CC
OPEN
GND
DIVIDER RATIO N
2
1
2
4
8
16
32
64
128
256
V
CC
V
CC
V
CC
OPEN
OPEN
OPEN
GND
GND
GND
Table 3. Divider Logic Setup
INPUT PIN
VSEL
VCO DIVIDER
N1
INPUT PIN
RSEL
REFERENCE-
CLOCK
DIVIDER N3
V
CC
OPEN
GND
4
8
32
V
CC
OPEN
GND
1
2
8
Table 2. RSEL and VSEL Settings
INPUT PIN GSEL
OPEN or V
CC
GND
Kpd (μA/UI)
20
5
Table 4. Phase Detector Gain Setup
INPUT PIN
PSEL1
V
CC
GND
V
CC
GND
INPUT PIN
PSEL2
V
CC
V
CC
GND
GND
VCO TO POUT
DIVIDER RATIO
1
2
4
8
Table 5. Optional Clock Setup
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MAX3675EHJ | 622Mbps, Low-Power, 3.3V Clock-Recovery and Data-Retiming IC with Limiting Amplifier |
| MAX3675 | 622Mbps, Low-Power, 3.3V Clock-Recovery and Data-Retiming IC with Limiting Amplifier |
| MAX3675ECJ | 622Mbps, Low-Power, 3.3V Clock-Recovery and Data-Retiming IC with Limiting Amplifier |
| MAX3676EHJ | 622Mbps, 3.3V Clock-Recovery and Data-Retiming IC with Limiting Amplifier |
| MAX3676 | 622Mbps, 3.3V Clock-Recovery and Data-Retiming IC with Limiting Amplifier |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MAX3672E/D | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MAX3672E/D DIE | 制造商:Maxim Integrated Products 功能描述: |
| MAX3673DBETN+ | 功能描述:時鐘合成器/抖動清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| MAX3673ETN | 功能描述:時鐘合成器/抖動清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| MAX3673ETN+ | 功能描述:時鐘合成器/抖動清除器 Low-Jitter Frequency Synthesizer RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。