- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄384665 > MAX3672 (Maxim Integrated Products, Inc.) Low-Jitter 155MHz/622MHz Clock Generator PDF資料下載
參數(shù)資料
| 型號： | MAX3672 |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | Low-Jitter 155MHz/622MHz Clock Generator |
| 中文描述： | 低抖動、155MHz/622MHz時鐘發(fā)生器 |
| 文件頁數(shù)： | 8/12頁 |
| 文件大?。?/td> | 493K |
| 代理商： | MAX3672 |
M
LOL
Detection Circuitry
The MAX3672 incorporates a loss-of-lock (
LOL
) monitor
that consists of an XOR gate, filter, and comparator with
adjustable threshold (see the
LOL
Setup
section). A
loss-of-lock condition is signaled with a TTL low when
the reference clock frequency differs from the VCO
frequency.
Phase-Frequency Detector and
Charge Pump
The phase-frequency detector incorporated into the
MAX3672 produces pulses proportional to the phase
difference between the reference clock and the VCO
input. The charge pump converts this pulse train to a
current signal that is fed to the op amp. The phase
detector gain can be set to either 5μA/UI or 20μA/UI
with the GSEL input (Table 4).
Op Amp
The op amp is used to form an active PLL loop filter
capable of driving the VCO control voltage input. Using
the POLAR input, the op amp input polarity can be select-
ed to work with VCOs having positive or negative gain-
transfer functions. The COMP pin selects the op amp
internal compensation. Connect COMP to ground if the
VCO control voltage is V
CC
referenced. Connect COMP
to V
CC
if the VCO control voltage is ground referenced.
Design Procedure
Setting Up the VCO and
Reference Clock
The MAX3672 accepts a range of reference clock and
VCO frequencies. The RSEL and VSEL inputs must be
set so that the output frequencies of the reference
clock and VCO pre-dividers are equal. Table 1 shows
the divider ratios and pre-divider output frequencies for
various reference clock and VCO frequencies.
Setting the Loop Bandwidth
To eliminate jitter present on the reference clock, the
proper selection of loop bandwidth is critical. If the total
output jitter is dominated by the noise at the reference
clock input, then lowering the loop bandwidth will
reduce system jitter. The loop bandwidth (K) is a func-
tion of the VCO gain (K
VCO
), the gain of the phase
detector (K
PD
), the loop filter resistor (R
1
), and the total
feedback-divider ratio (N = N1
N2). The loop band-
width of the MAX3672 can be approximated by:
For stability, a zero must be added to the loop in the form
of resistor R
1
in series with capacitor C
1
(see the
Functional Diagram
). The location of the zero can be
approximated as:
Because of the second-order nature of the PLL jitter
transfer, peaking will occur and is proportional to f
Z
/K.
For certain applications, it may be desirable to limit jitter
peaking in the PLL passband region to less than 0.1dB.
This can be achieved by setting f
Z
≤
K/100.
A more detailed analysis of the loop filter is located in
application note HFDN-13.0 on www.maxim-ic.com.
f
R C
π
Z
=
1
2
K
K
RK
π
2
N
PD
VCO
=
Low-Jitter 155MHz/622MHz Clock Generator
8
_______________________________________________________________________________________
F
VOC
(MHz)
F
REF
(MHz)
VSEL INPUT
VCO
DIVIDER N1
RSEL
INPUT
REFERENCE-
CLOCK DIVIDER N3
PRE-DIVIDER
OUTPUT FREQUENCY
(MHz)
622.08
622.08
622.08
622.08
155.52
155.52
155.52
155.52
622.08
155.52
77.76
19.44
622.08
155.52
77.76
19.44
OPEN
OPEN
OPEN
GND
—
OPEN
V
CC
OPEN
8
8
8
32
—
8
4
8
GND
OPEN
V
CC
V
CC
—
GND
OPEN
V
CC
8
2
1
1
—
8
2
1
77.76
77.76
77.76
19.44
––
19.44
38.88
19.44
Table 1. VCO and Reference Clock Setup
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MAX3675EHJ | 622Mbps, Low-Power, 3.3V Clock-Recovery and Data-Retiming IC with Limiting Amplifier |
| MAX3675 | 622Mbps, Low-Power, 3.3V Clock-Recovery and Data-Retiming IC with Limiting Amplifier |
| MAX3675ECJ | 622Mbps, Low-Power, 3.3V Clock-Recovery and Data-Retiming IC with Limiting Amplifier |
| MAX3676EHJ | 622Mbps, 3.3V Clock-Recovery and Data-Retiming IC with Limiting Amplifier |
| MAX3676 | 622Mbps, 3.3V Clock-Recovery and Data-Retiming IC with Limiting Amplifier |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MAX3672E/D | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MAX3672E/D DIE | 制造商:Maxim Integrated Products 功能描述: |
| MAX3673DBETN+ | 功能描述:時鐘合成器/抖動清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| MAX3673ETN | 功能描述:時鐘合成器/抖動清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| MAX3673ETN+ | 功能描述:時鐘合成器/抖動清除器 Low-Jitter Frequency Synthesizer RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。