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參數(shù)資料
| 型號： | MAX3672 |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | Low-Jitter 155MHz/622MHz Clock Generator |
| 中文描述： | 低抖動、155MHz/622MHz時鐘發(fā)生器 |
| 文件頁數(shù)： | 7/12頁 |
| 文件大?。?/td> | 493K |
| 代理商： | MAX3672 |
Detailed Description
The MAX3672 contains all the blocks needed to form a
PLL except for the VCO, which must be supplied sepa-
rately. The MAX3672 consists of input buffers for the ref-
erence clock and VCO, input and output clock-divider
circuitry, LOL detection circuitry phase detector, gain-
control logic, a phase-frequency detector and charge
pump, an op amp, and PECL output buffers.
This device is designed to clean up the noise on the ref-
erence clock input and provide a low-jitter system clock
output. This device also supports frequency conversion.
Input Buffer for Reference
Clock and VCO
The MAX3672 contains differential inputs for the refer-
ence clock and the VCO. These high impedance inputs
can be DC-coupled and are internally biased with so
that they can be AC-coupled (Figure 1 in the
Interface
Schematic
section). A single-ended VCO or reference
clock can also be applied.
Input and Output Clock-Divider Circuitry
The pre-dividers scale the input frequencies of the VCO
and reference clock. Clock-divider ratios N1 and N3
must be chosen so that the output frequencies of the
pre-dividers are equal. The maximum allowable pre-
divider output frequency is 77.76MHz (Table 1).
The main dividers (N2) facilitate tuning the loop band-
width by setting the frequency divider ratio. The divider
control logic can be programmed to divide from 1 to 256
in binary multiples (Table 3). The POUT output buffer is
preceded by a clock divider that scales the main clock
output by 1, 2, 4, or 8 to provide an optional clock.
M
Low-Jitter 155MHz/622MHz Clock Generator
_______________________________________________________________________________________
7
MAX3672
OPAMP
DIV (N3)
1/2/8
PECL
VCO
K
VCO
REFCLK-
RSEL
REFCLK+
C3
LOL
THADJ
CTH
VC
COMP
POLAR
OPAMP-
OPAMP+
R3
C1
C1
R1
R1
DIV (N1)
4/8/32
DIVIDER
CONTROL LOGIC
PECL
VCOIN-
NSEL1
NSEL2
PSEL1
PSEL2
VFILTER
VSEL
VCOIN+
DIV
(N2)
PFD/CP
Kpd
GSEL
MOUT+
MOUT-
C2-
C2+
LOL
DIV
(N2)
PECL
POUT+
POUT-
PECL
DIV
1/2/4/8
Functional Diagram
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MAX3672E/D | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MAX3672E/D DIE | 制造商:Maxim Integrated Products 功能描述: |
| MAX3673DBETN+ | 功能描述:時鐘合成器/抖動清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| MAX3673ETN | 功能描述:時鐘合成器/抖動清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| MAX3673ETN+ | 功能描述:時鐘合成器/抖動清除器 Low-Jitter Frequency Synthesizer RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
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