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參數(shù)資料
| 型號(hào)： | MAX3270EMH |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | 32-Bit Digital Signal Controller with Flash 100-BGA MICROSTAR -40 to 125 |
| 中文描述： | CLOCK RECOVERY CIRCUIT, PQFP44 |
| 封裝： | MQFP-44 |
| 文件頁(yè)數(shù)： | 9/12頁(yè) |
| 文件大?。?/td> | 101K |
| 代理商： | MAX3270EMH |
Input and Output T ermination
The MAX3270 data and clock I/Os (SDIP, SDIN, RDOP,
RDON, RCOP, RCON, and EXC) are open emitters,
designed to interface with ECL signal levels. It is impor-
tant to bias these ports appropriately. A circuit that pro-
vides a Thevenin equivalent of 50
to -2V should be
used with fixed-impedance transmission lines for prop-
er termination. Figure 4 shows some typical input and
output termination methods.
The serial data input signals (SDIP and SDIN) are the
differential inputs to an emitter coupled pair. As a result,
the MAX3270 can accept differential input signal levels
as low as 250mV. The serial input (SDIP) can also be
driven single-ended by externally biasing SDIN to the
center of the voltage swing (approximately -1.3V). Make
sure that the differential inputs and outputs each see the
same termination impedance for balanced operation.
CRP is also an open-emitter ECL output, but it requires
a termination resistor of 450
to -4.5V. If this output is
not used, reduce power by connecting CRP to V
EE
through a resistor valued at 10k
or more.
The MAX3270’s performance can be greatly affected
by circuit board layout and design. Use good high-fre-
quency design techniques, including minimizing
ground inductances and using fixed-impedance trans-
mission lines on the data and clock signals. Power-
supply decoupling should be placed as close to the
VEE and VTTL pins as possible. AVEE1, AVEE2 and
GVEE should each have their own bypass/decoupling
elements, independent of each other and any other -
4.5V supply. Make sure to isolate the inputs from the
outputs to reduce feedthrough.
__________Applic ations Information
Loc k Detec tion
The MAX3270 has an output (FM) that monitors the input
voltage to the VCO. FM is an analog output that can be
used as a flag to indicate that the PLL is locked. Under
normal operation, the loop is locked and the FM output
is approximately equal to 0V. When the PLL is unlocked,
the VCO will drift. The FM output monitors this drift and
will equal approximately ±1V in the limit.
Phase Adjust
In some applications, the optimum alignment point
between the recovered clock and the serial data is not
at the center of the eye diagram. The MAX3270 has a
PHADJ input that can be used in these applications to
introduce a phase difference between the recovered
clock and the serial data. When no phase difference is
desired, this input should be set to 0V. The VR pin is the
reference input for PHADJ and is normally tied to GND.
M
155Mbps/622Mbps Cloc k Rec overy and
Data Retiming IC with Fully Integrated
Phase/Frequenc y Detec tor
_______________________________________________________________________________________
9
90.9
90.9
111
450
111
Zo = 50
Zo = 50
90.9
90.9
111
111
Zo = 50
Zo = 50
-4.5V
-4.5V
-4.5V
50
450
50
Zo = 50
Zo = 50
50
50
Zo = 50
Zo = 50
-2V
-4.5V
-2V
MAX3270
MAX3270
ECL
INPUTS
ECL
OUTPUTS
CRP
CRP
ECL
INPUTS
ECL
OUTPUTS
50
to -2V TERMINATION
THEVENIN EQUIVALENT TERMINATION
Figure 4. Typical Input and Output Terminations
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| MAX3270EMH-T | 功能描述:模擬開關(guān) IC RoHS:否 制造商:Texas Instruments 開關(guān)數(shù)量:2 開關(guān)配置:SPDT 開啟電阻（最大值）:0.1 Ohms 切換電壓（最大）: 開啟時(shí)間（最大值）: 關(guān)閉時(shí)間（最大值）: 工作電源電壓:2.7 V to 4.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-16 |
| MAX3271E/D | 功能描述:模擬開關(guān) IC RoHS:否 制造商:Texas Instruments 開關(guān)數(shù)量:2 開關(guān)配置:SPDT 開啟電阻（最大值）:0.1 Ohms 切換電壓（最大）: 開啟時(shí)間（最大值）: 關(guān)閉時(shí)間（最大值）: 工作電源電壓:2.7 V to 4.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-16 |
| MAX3271E/D DIE | 制造商:Maxim Integrated Products 功能描述: |
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| MAX3272AEGP | 功能描述:限幅放大器 3.3V 2.5Gbps Limiting Amplifier RoHS:否 制造商:Micrel 輸入電壓范圍（最大值）:3.6 V 工作電源電壓:3.3 V 電源電流:40 mA 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:MSOP-10 封裝:Tube |
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