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參數(shù)資料
| 型號(hào)： | MAX3270EMH |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | 32-Bit Digital Signal Controller with Flash 100-BGA MICROSTAR -40 to 125 |
| 中文描述： | CLOCK RECOVERY CIRCUIT, PQFP44 |
| 封裝： | MQFP-44 |
| 文件頁數(shù)： | 8/12頁 |
| 文件大?。?/td> | 101K |
| 代理商： | MAX3270EMH |
M
__________________Design Proc edure
S elec ting the Data Rate
The MAX3270 is intended for use in SDH/SONET sys-
tems operating at 155.52Mbps or 622.08Mbps data
rates. TTL inputs (CRS and EXCS) are provided for
selecting the recovered clock rate (Table 1). It is also
possible to switch to an externally supplied clock by
enabling the EXC input. The EXC input is a high-speed
single-ended ECL interface capable of handling serial
clock rates of 155MHz and 622MHz.
S etting the Loop Filter
The loop filter within the PLL consist of a transconduc-
tance amplifier and the external filter elements Rf and
Cf (Figure 2). The closed-loop bandwidth of a PLL can
be approximated by:
K
D
K
O
Gm Rf
where K
D
is the gain of the phase detector, KO is the
gain of the VCO, and Gm is the transconductance of
the filter amplifier. Because this filter is an integrator, a
zero in the open-loop gain is required for stability. This
zero is set by the following equation:
w
z
= 1 / (Rf Cf)
where the recommended external values are Rf = 20
and Cf = 2.2μF. To decrease the PLL’s closed-loop
bandwidth, reduce the value of Rf. Decreasing this
bandwidth will improve the MAX3270’s jitter transfer
performance but reduce jitter tolerance. The MAX3270
has been designed (using the recommended values of
Rf and Cf) to meet the Bellcore and CCITT specifica-
tions for jitter tolerance of a Network Element. Carefully
consider the application if a reduction in loop band-
width is desired. By reducing Rf an order of magnitude,
the PLL’s bandwidth becomes more sensitive to the
internal tolerances of the IC. As a result, the loop band-
width may have a wider variation. If Rf is reduced, then
Cf should also be increased to maintain loop stability
and minimize jitter peaking.
The MAX3270 is optimally designed to acquire lock
and to provide a bit-error rate (BER) of less than 10
-12
for long strings of consecutive zeros or ones. Using the
recommended external values for Rf = 20
and Cf =
2.2μF, measured results show that the MAX3270 can
tolerate more than 200 consecutive ones or zeros.
Figure 3 shows a bit stream of 2
13
- 1 PRBS with 200
consecutive ones.
155Mbps/622Mbps Cloc k Rec overy and
Data Retiming IC with Fully Integrated
Phase/Frequenc y Detec tor
8
_______________________________________________________________________________________
Table 1. MAX3270 Logic Table
EXCS
CRS
RCOP/RCON
CRP
0
1
155.52Mbps
38.88Mbps
0
0
622.08Mbps
155.52Mbps
1
0
EXC
EXC/4
1
1
EXC/4
EXC/16
100ns/div
2.532μs
1.532μs
RECOVERED DATA OUTPUT
(2
13
-1 PRBBER <10-
12
, 622Mbps)
PRBS
200 ONES
MAX3270
FILP
FILG
FILN
Rf
Cf
Rf
Cf
F(s) = Gm
wz = Rf Cf
Rf = 20
Cf = 2.2
μ
F
(
wz
)
s
Gm
F(s)
Figure 2. Loop Filter
Figure 3. Recovered Data Output
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| MAX3270EMH-T | 功能描述:模擬開關(guān) IC RoHS:否 制造商:Texas Instruments 開關(guān)數(shù)量:2 開關(guān)配置:SPDT 開啟電阻（最大值）:0.1 Ohms 切換電壓（最大）: 開啟時(shí)間（最大值）: 關(guān)閉時(shí)間（最大值）: 工作電源電壓:2.7 V to 4.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-16 |
| MAX3271E/D | 功能描述:模擬開關(guān) IC RoHS:否 制造商:Texas Instruments 開關(guān)數(shù)量:2 開關(guān)配置:SPDT 開啟電阻（最大值）:0.1 Ohms 切換電壓（最大）: 開啟時(shí)間（最大值）: 關(guān)閉時(shí)間（最大值）: 工作電源電壓:2.7 V to 4.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-16 |
| MAX3271E/D DIE | 制造商:Maxim Integrated Products 功能描述: |
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