參數(shù)資料
型號(hào): MAX3270EMH
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: 數(shù)字傳輸電路
英文描述: 32-Bit Digital Signal Controller with Flash 100-BGA MICROSTAR -40 to 125
中文描述: CLOCK RECOVERY CIRCUIT, PQFP44
封裝: MQFP-44
文件頁(yè)數(shù): 6/12頁(yè)
文件大?。?/td> 101K
代理商: MAX3270EMH
M
155Mbps/622Mbps Cloc k Rec overy and
Data Retiming IC with Fully Integrated
Phase/Frequenc y Detec tor
6
_______________________________________________________________________________________
______________________________________________________________Pin Desc ription
Loop Filter Positive. This pin connects to an external filter.
Loop Filter Negative. This pin connects to an external filter.
TTL Positive Supply: +5.0V
Negative Supply for VCO: -4.5V
External Clock-Select TTL Input. A logical high selects the external clock.
External Clock. Single-ended ECL input.
Ground for VCO: 0V
FILP
FILN
VTTL
AVEE2
EXCS
EXC
AVCC
9
10
11
12
13
14
Ground for Input Buffers: 0V
AVCC
5
Frequency Monitor Output. This pin monitors the input voltage to the VCO. When the PLL is locked,
the pin will be
0V.
FM
6
Guard-Ring Positive Supply to Epi: 0V
Loop Filter Ground. This pin connects to an external filter.
AVCC
FILG
7
8
Serial Data Input: 155Mbps or 622Mbps. Differential ECL Negative.
SDIN
4
Serial Data Input: 155Mbps or 622Mbps. Differential ECL Positive.
SDIP
3
PIN
1
Negative Supply for Input Buffers: -4.5V
AVEE1
2
Guard-Ring Negative Supply to Substrate: -4.5V
GVEE
FUNCTION
NAME
15, 16
17, 19, 38,
39
DVCC
Digital Ground for Mux: 0V
18
CRS
Clock-Rate Select TTL Input. This selects the clock rate to be either 155Mbps or 622Mbps. A logic-
high level selects the 622Mbps mode.
20
RST
Resets all digital flip-flops, TTL input. Reset is assert when low.
21, 22, 34,
35, 36
DVEE
Digital Negative Supply: -4.5V
23, 33, 37,
40, 43, 44
N.C.
No Connection
24, 27, 29,
32
OVCC
Output Driver Ground: 0V
25
26
28
30
31
RDON
RDOP
CRP
RCON
RCOP
Negative Recovered Data Output, differential ECL output: 155Mbps or 622Mbps.
Positive Recovered Data Output, differential ECL output: 155Mbps or 622Mbps.
Clock-Reference Output Divide-by-4. ECL low-power single-ended: 38Mbps or 155Mbps.
Negative Recovered Clock Output, differential ECL output: 155Mbps or 622Mbps.
Positive Recovered Clock Output, differential ECL output: 155Mbps or 622Mbps.
41
PHADJ
Phase Adjust. This is an analog adjustment that varies the static phase between the input data and
the recovered clock. If not used, this input should be grounded. The range is from -1V to 1V.
42
VR
Phase Reference Voltage: 0V. The PHADJ pin compares to this voltage. Set to ground.
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MAX3271E/D DIE 制造商:Maxim Integrated Products 功能描述:
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