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參數(shù)資料
| 型號： | MAX19713ETN |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | 10-Bit, 45Msps, Full-Duplex Analog Front-End |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, QCC56 |
| 封裝： | 7 X 7 MM, 0.80 MM HEIGHT, MO-220, TQFN-56 |
| 文件頁數(shù)： | 25/37頁 |
| 文件大?。?/td> | 892K |
| 代理商： | MAX19713ETN |
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M
Figure 6. Serial-Interface Timing Diagram
t
CSW
t
CS
LSB
t
CL
t
CP
t
CH
t
DH
t
DS
MSB
t
CSS
SCLK
DIN
CS/WAKE
10-Bit, 45Msps, Full-Duplex
Analog Front-End
______________________________________________________________________________________
25
QSPI is a trademark of Motorola, Inc.
Figure 7. Mode-Recovery Timing Diagram
CS/WAKE
SCLK
DIN
16-BIT SERIAL DATA INPUT
AD0–AD9
ID/QD
DAC ANALOG OUTPUT
SETTLES TO 10 LSB ERROR
t
WAKE,SD,ST_
TO Tx MODE OR t
ENABLE
,
TX
ADC DIGITAL OUTPUT SINAD
SETTLES TO WITHIN 1dB
t
WAKE,SD,ST_
TO Rx MODE OR t
ENABLE
,
RX
MAX19713 enters the power mode determined by the
WAKEUP-SEL register, however, all other settings (Tx
DAC offset, Tx DAC common-mode voltage, aux-DAC
settings, aux-ADC state) are restored to their values
prior to shutdown.
The only SPI line that is monitored by the MAX19713
during shutdown is
CS
/WAKE. Any information transmit-
ted to the MAX19713 concurrent with the
CS
/WAKE
wake-up pulse is ignored.
SPI Timing
The serial digital interface is a standard 3-wire connection
(
CS
/WAKE, SCLK, DIN) compatible with SPI/QSPI/
MICROWIRE/DSP interfaces. Set
CS
/WAKE low to enable
the serial data loading at DIN or output at DOUT.
Following a
CS
/WAKE high-to-low transition, data is shift-
ed synchronously, most significant bit first, on the rising
edge of the serial clock (SCLK). After 16 bits are loaded
into the serial input register, data is transferred to the latch
when
CS
/WAKE transitions high.
CS
/WAKE must transi-
tion high for a minimum of 80ns before the next write
sequence. SCLK can idle either high or low between tran-
sitions. Figure 6 shows the detailed timing diagram of the
3-wire serial interface.
Mode-Recovery Timing
Figure 7 shows the mode-recovery timing diagram.
t
WAKE
is the wake-up time when exiting shutdown, idle,
or standby mode and entering Rx, Tx, or FD mode.
t
ENABLE
is the recovery time when switching between
either Rx or Tx mode. t
WAKE
or t
ENABLE
is the time for
the Rx ADC to settle within 1dB of specified SINAD per-
formance and Tx DAC settling to 10 LSB error. t
WAKE
and t
ENABLE
times are measured after the 16-bit serial
command is latched into the MAX19713 by a
CS
/WAKE
transition high. In FAST mode, the recovery time is 0.1μs
to switch between Tx or Rx modes.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MAX19713ETN+ | 功能描述:ADC / DAC多通道 45Msps CODEC/AFE Full Duplex RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換速率: 分辨率:8 bit 接口類型:SPI 電壓參考: 電源電壓-最大:3.6 V 電源電壓-最小:2 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-40 |
| MAX19713ETN+GH7 | 功能描述:ADC / DAC多通道 10-Bit 45Msps Full-Duplex Analog Front-End RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換速率: 分辨率:8 bit 接口類型:SPI 電壓參考: 電源電壓-最大:3.6 V 電源電壓-最小:2 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-40 |
| MAX19713ETN+T | 功能描述:ADC / DAC多通道 45Msps CODEC/AFE Full Duplex RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換速率: 分辨率:8 bit 接口類型:SPI 電壓參考: 電源電壓-最大:3.6 V 電源電壓-最小:2 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-40 |
| MAX19713ETN+TGH7 | 功能描述:ADC / DAC多通道 10-Bit 45Msps Full-Duplex Analog Front-End RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換速率: 分辨率:8 bit 接口類型:SPI 電壓參考: 電源電壓-最大:3.6 V 電源電壓-最小:2 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-40 |
| MAX19713ETN-T | 功能描述:ADC / DAC多通道 RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換速率: 分辨率:8 bit 接口類型:SPI 電壓參考: 電源電壓-最大:3.6 V 電源電壓-最小:2 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-40 |
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