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參數(shù)資料
| 型號(hào)： | MAX189CEWE+T |
| 廠商： | Maxim Integrated Products |
| 文件頁(yè)數(shù)： | 6/18頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT SERIAL LP 16SOIC |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 75k |
| 數(shù)據(jù)接口： | MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 478mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SOIC W |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個(gè)單端，單極 |
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MAX187/MAX189
+5V, Low-Power, 12-Bit Serial ADCs
14
Maxim Integrated
QSPI
Set CPOL = CPHA = 0. Unlike SPI, which requires two
1-byte reads to acquire the 12 bits of data from the ADC,
QSPI allows the minimum number of clock cycles neces-
sary to clock in the data. The MAX187/MAX189 require
13 clock cycles from the FP to clock out the 12 bits of
data with no trailing 0s (Figure 15). The maximum clock
frequency to ensure compatibility with QSPI is 2.77MHz.
Opto-Isolated Interface,
Serial-to-Parallel Conversion
Many industrial applications require electrical isolation to
separate the control electronics from hazardous electri-
cal conditions, provide noise immunity, or prevent exces-
sive current flow where ground disparities exist between
the ADC and the rest of the system. Isolation amplifiers
typically used to accomplish these tasks are expensive.
In cases where the signal is eventually converted to a
digital form, it is cost effective to isolate the input using
opto-couplers in a serial link.
The MAX187 is ideal in this application because it includes
both T/H amplifier and voltage reference, operates from a
single supply, and consumes very little power (Figure 16).
The ADC results are transmitted across a 1500V isolation
barrier provided by three 6N136 opto-isolators. Isolated
power must be supplied to the converter and the isolated
side of the opto-couplers. 74HC595 three-state shift reg-
isters are used to construct a 12-bit parallel data output.
The timing sequence is identical to the timing shown
in Figure 8. Conversion speed is limited by the delay
through the opto-isolators. With a 140kHz clock, conver-
sion time is 100Fs.
The universal 12-bit parallel data output can also be used
without the isolation stage when a parallel interface is
required. Clock frequencies up to 2.9MHz are possible
without violating the 20ns shift-register setup time. Delay or
invert the clock signal to the shift registers beyond 2.9MHz.
Figure 14. SPI/MICROWIRE Serial Interface Timing (CPOL = CPHA = 0)
Figure 13. Common Serial-Interface Connections to the
MAX187/MAX189
MSB
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
LSB
HI-Z
tCONV
DOUT
CS
SCLK
HI-Z
EOC
2ND BYTE READ
1ST BYTE READ
MAX187
MAX189
CS
SCLK
DOUT
I/O
SCK
MISO
+5V
SS
A. SPI
MAX187
MAX189
CS
SCLK
DOUT
CS
SCK
MISO
+5V
SS
B. QSPI
MAX187
MAX189
CS
SCLK
DOUT
I/O
SK
SI
C. MICROWIRE
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