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參數(shù)資料
| 型號： | MAX189CEWE+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 2/18頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT SERIAL LP 16SOIC |
| 產(chǎn)品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 1,000 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 75k |
| 數(shù)據(jù)接口： | MICROWIRE?，QSPI?，串行，SPI? |
| 轉換器數(shù)目： | 1 |
| 功率耗散（最大）： | 478mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.295"，7.50mm 寬） |
| 供應商設備封裝： | 16-SOIC W |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個單端，單極 |
MAX187/MAX189
+5V, Low-Power, 12-Bit Serial ADCs
10
Maxim Integrated
Figure 6. Average Supply Current vs. Conversion Rate
Figure 7. tWAkE vs. Time in Shutdown (MAX187 Only)
Serial Interface
Initialization After Power-Up and
Starting a Conversion
When power is first applied, it takes the fully discharged
4.7FF reference bypass capacitor up to 20ms to provide
adequate charge for specified accuracy. With SHDN
not pulled low, the MAX187/MAX189 are now ready to
convert.
To start a conversion, pull CS low. At CS’s falling edge,
the T/H enters its hold mode and a conversion is initiated.
After an internally timed 8.5Fs conversion period, the end
of conversion is signaled by DOUT pulling high. Data can
then be shifted out serially with the external clock.
Using SHDN to Reduce
Supply Current
Power consumption can be reduced significantly by
shutting down the MAX187/MAX189 between conver-
sions. This is shown in Figure 6, a plot of average supply
current vs. conversion rate. Because the MAX189 uses
an external reference voltage (assumed to be present
continuously), it “wakes up” from shutdown more quickly,
and therefore provides lower average supply currents.
The wakeup-time, tWAKE, is the time from SHDN deas-
serted to the time when a conversion may be initiated.
For the MAX187, this time is 2Fs. For the MAX189, this
time depends on the time in shutdown (see Figure 7)
because the external 4.7FF reference bypass capacitor
loses charge slowly during shutdown (see the specifica-
tions for shutdown, REF Input Current = 10FA max).
External Clock
The actual conversion does not require the external
clock. This frees the FP from the burden of running the
SAR conversion clock, and allows the conversion result
to be read back at the FP’s convenience at any clock rate
from 0 to 5MHz. The clock duty cycle is unrestricted if
each clock phase is at least 100ns. Do not run the clock
while a conversion is in progress.
Timing and Control
Conversion-start and data-read operations are controlled
by the CS and SCLK digital inputs. The timing diagrams
of Figures 8 and 9 outline the operation of the serial
interface.
A CS falling edge initiates a conversion sequence: The
T/H stage holds input voltage, the ADC begins to convert,
and DOUT changes from high impedance to logic low.
SCLK must be kept inactive during the conversion. An
internal register stores the data when the conversion is
in progress.
End of conversion (EOC) is signaled by DOUT going
high. DOUT’s rising edge can be used as a framing sig-
nal. SCLK shifts the data out of this register any time after
the conversion is complete. DOUT transitions on SCLK’s
falling edge. The next falling clock edge produces the
MSB of the conversion at DOUT, followed by the remain-
ing bits. Since there are 12 data bits and one leading
high bit, at least 13 falling clock edges are needed to
shift out these bits. Extra clock pulses occurring after the
conversion result has been clocked out, and prior to a
rising edge of CS, produce trailing 0s at DOUT and have
no effect on converter operation.
CONVERSIONS PER SECOND
SUPPLY
CURRENT
(A)
10k
1k
100
10
1
10
100
1000
10,000
1
0.1
100k
MAX187
MAX189*
*REF CONNECTED TO VDD
TIME IN SHUTDOWN (s)
t WAKE
(ms)
1
0.1
0.01
0.001
0.5
1.0
1.5
2.0
2.5
3.0
0
0.0001
10
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