參數(shù)資料
型號: IDT72T7285L4-4BBG
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 1/53頁
文件大?。?/td> 0K
描述: IC FIFO 16384X72 4.4NS 324BGA
標準包裝: 1
系列: 72T
訪問時間: 3.2ns
電源電壓: 2.375 V ~ 2.625 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 324-BGA
供應商設(shè)備封裝: 324-PBGA(19x19)
包裝: 托盤
1
FEBRUARY 2009
DSC-5994/15
2009 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The TeraSync FIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
2.5 VOLT HIGH-SPEED TeraSyncTM FIFO 72-BIT CONFIGURATIONS
16,384 x 72, 32,768 x 72,
65,536 x 72, 131,072 x 72
IDT72T7285, IDT72T7295,
IDT72T72105, IDT72T72115
FUNCTIONAL BLOCK DIAGRAM
INPUT REGISTER
OUTPUT REGISTER
RAM ARRAY
16,384 x 72
32,768 x 72
65,536 x 72
131,072 x 72
FLAG
LOGIC
FF/IR
PAF
EF/OR
PAE
HF
READ POINTER
READ
CONTROL
LOGIC
WRITE CONTROL
LOGIC
WRITE POINTER
RESET
LOGIC
WEN WCLK/WR
D0 -Dn (x72, x36 or x18)
LD
MRS
REN
RCLK/RD
OE
Q0 -Qn (x72, x36 or x18)
OFFSET REGISTER
PRS
FWFT/SI
SEN
RT
5994 drw01
BUS
CONFIGURATION
BM
CONTROL
LOGIC
BE
OW
IP
PFM
FSEL0
FSEL1
IW
MARK
SCLK
RCS
JTAG CONTROL
(BOUNDARY SCAN)
TCK
TMS
TDO
TDI
TRST
ASYR
WCS
ERCLK
EREN
HSTL I/0
CONTROL
Vref
WHSTL
RHSTL
ASYW
SHSTL
FEATURES:
Choose among the following memory organizations:
IDT72T7285
16,384 x 72
IDT72T7295
32,768 x 72
IDT72T72105
65,536 x 72
IDT72T72115
131,072 x 72
Up to 225 MHz Operation of Clocks
User selectable HSTL/LVTTL Input and/or Output
Read Enable & Read Clock Echo outputs aid high speed operation
User selectable Asynchronous read and/or write port timing
2.5V LVTTL or 1.8V, 1.5V HSTL Port Selectable Input/Ouput voltage
3.3V Input tolerant
Mark & Retransmit, resets read pointer to user marked position
Write Chip Select (WCS) input disables Write Port HSTL inputs
Read Chip Select (RCS) synchronous to RCLK
Programmable Almost-Empty and Almost-Full flags, each flag can
default to one of eight preselected offsets
Program programmable flags by either serial or parallel means
Selectable synchronous/asynchronous timing modes for Almost-
Empty and Almost-Full flags
Separate SCLK input for Serial programming of flag offsets
User selectable input and output port bus-sizing
- x72 in to x72 out
- x72 in to x36 out
- x72 in to x18 out
- x36 in to x72 out
- x18 in to x72 out
Big-Endian/Little-Endian user selectable byte representation
Auto power down minimizes standby power consumption
Master Reset clears entire FIFO
Partial Reset clears data, but retains programmable settings
Empty, Full and Half-Full flags signal FIFO status
Select IDT Standard timing (using EF and FF flags) or First Word
Fall Through timing (using
OR and IR flags)
Output enable puts data outputs into high impedance state
JTAG port, provided for Boundary Scan function
Available in 324-pin (19mm x 19mm)Plastic Ball Grid Array (PBGA)
Easily expandable in depth and width
Independent Read and Write Clocks (permit reading and writing
simultaneously)
High-performance submicron CMOS technology
Industrial temperature range (–40
°°°°°C to +85°°°°°C) is available
Green parts are available, see ordering information
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