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參數(shù)資料
| 型號(hào)： | MAX1455EVKIT-NS |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 4/25頁 |
| 文件大?。?/td> | 0K |
| 描述： | EVAL KIT FOR MAX1455 |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 接口，傳感器信號(hào)調(diào)節(jié)器 |
| 已用 IC / 零件： | MAX1455 |
| 已供物品： | 板 |
MAX1455
Serial Interface Command Format
All communication commands into the MAX1455 follow
the format of a start bit, 8 command bits (command
byte), and a stop bit. The Command Byte controls the
contents of the IRS and comprises a 4-bit interface reg-
ister set address (IRSA) nibble and a 4-bit interface
register set data (IRSD) nibble. The IRS Command Byte
is structured as follows:
IRS[7:0] = IRSD[3:0], IRSA[3:0]
All commands are transmitted LSB first. The first bit fol-
lowing the start bit is IRSA[0] and the last bit before the
stop bit is IRSD[3] as follows:
Half of the register contents of the IRS are used for data
hold and steering information. Data writes to two loca-
tions within the IRS cause immediate action (command
execution). These locations are at addresses 9 and 15
and are the Command Register to Internal Logic (CRIL)
and reinitialize commands, respectively. Table 9 shows
a full listing of IRS address decoding.
Command sequences can be written to the MAX1455
as a continuous stream, i.e., start bit, command byte,
stop bit, start bit, command byte, stop bit, etc. There
are no delay requirements between commands while
the MAX1455 is receiving data.
Command Register to Internal Logic
A data write to the CRIL location (IRS address 9) causes
immediate execution of the command associated with
the 4-bit data nibble written. All EEPROM and Calibration
register read and write, together with EEPROM erase,
commands are handled through the CRIL location. CRIL
is also used to enable the MAX1455 analog output and
to place output data (serial digital output) on DIO. Table
10 shows a full listing of CRIL commands.
IRSA
IRSD
11111
0
01230
123
1
11
111
Low-Cost Automotive Sensor Signal
Conditioner
12
______________________________________________________________________________________
Table 5. Configuration Register (CONFIG[15:0])
FIELD
NAME
DESCRIPTION
15:13
OSC[2:0]
Oscillator frequency setting. Factory preset; do not change.
12:11
CLIP[1:0]
Sets output clip levels.
10
PGA Sign
Logic 1 inverts INM and INP polarity (Table 6).
9
IRO Sign
Logic 1 for positive input-referred offset (IRO). Logic 0 for negative IRO.
8:6
IRO[2:0]
Input-referred coarse-offset adjustment (Table 7).
5:2
PGA[3:0]
Programmable-gain amplifier setting.
1
ODAC Sign
Logic 1 for positive offset DAC output. Logic 0 for negative offset DAC output.
0
OTCDAC
Sign
Logic 1 for positive offset TC DAC output. Logic 0 for negative offset TC DAC output.
Table 6. PGA Gain Setting (PGA[3:0])
PGA[3:0]
PGA GAIN (V/V)
0000
39
0001
52
0010
65
0011
78
0100
91
0101
104
0110
117
0111
130
1000
143
1001
156
1010
169
1011
182
1100
195
1101
208
1110
221
1111
234
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