參數(shù)資料
型號(hào): MAX1441GUP/V+
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 21/41頁(yè)
文件大?。?/td> 0K
描述: IC PROXMITY SENSOR 2CH 20-TSSOP
其它有關(guān)文件: Automotive Product Guide
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 74
類型: 觸控式傳感器
輸入類型: 數(shù)字
輸出類型: 數(shù)字
接口: JTAG,串行
電流 - 電源: 100µA
安裝類型: 表面貼裝
封裝/外殼: 20-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 20-TSSOP
包裝: 管件
MAX1441
Automotive, Two-Channel Proximity and
Touch Sensor
28
Table 11. Special-Function Register Bit Description (continued)
REGISTER
DESCRIPTION
WU1.1–RE1
CH1 Rate-of-Change Wake-Up Threshold Enable. Setting this bit to 1 enables the rate-of-change
wake-up threshold detection. Clearing this bit to 0 disables the rate-of-change wake-up threshold
detection.
WU1.2–AO1
CH1 AND/OR Mode Enable. Setting this bit to 1 causes an interrupt to the CPU when both the absolute
and rate-of-change threshold are exceeded. Both AEI and REI must be enabled when AO1 is set to 1.
Clearing this bit to 0 causes an interrupt to the CPU when either the absolute threshold or rate-of-change
threshold is exceeded.
WU1[7:3]
Reserved. Read returns 0.
WU2 (05h, 01h)
Channel 2 Wake-Up Control Register (8-Bit Register)
Initialization
This register is cleared to 04h on all forms of reset.
Read/Write Access
Unrestricted read/write.
WU2.0–AE2
CH2 Absolute Wake-Up Threshold Enable. Setting this bit to 1 enables the absolute wake-up
threshold detection. Clearing this bit to 0 disables the absolute wake-up threshold detection.
WU2.1–RE2
CH2 Rate-of-Change Wake-Up Threshold Enable. Setting this bit to 1 enables the rate-of-change
wake-up threshold detection. Clearing this bit to 0 disables the rate-of-change wake-up threshold
detection.
WU2.2–AO2
CH2 AND/OR Mode Enable. Setting this bit to 1 causes an interrupt to the CPU when both the absolute
and rate-of-change threshold are exceeded. Clearing this bit to 0 causes an interrupt to the CPU when
either the absolute or rate-of-change threshold is exceeded.
WU2[7:3]
Reserved. Read returns 0.
FEL (06h, 01h)
Excitation Frequency Low-Limit Register (8-Bit Register)
Initialization
This register is set to 1Eh on all forms of reset.
Read/Write Access
Unrestricted read/write.
FEL[5:0]
Excitation Frequency Low-Limit Bits [5:0]. These bits set the lower end of the excitation frequency
(FEL x 10kHz).
FEL[7:6]
Reserved. Read returns 0.
FEB (07h, 01h)
Excitation Frequency Spread-Spectrum Bandwidth Register (8-Bit Register)
Initialization
This register is cleared to 00h on all forms of reset.
Read/Write Access
Unrestricted read/write.
FEB[4:0]
Excitation Frequency Spread-Spectrum Bandwidth Bits [4:0]. These bits set the excitation frequency
bandwidth (FEB x 20kHz).
FEB[7:5]
Reserved. Read returns 0.
CRSLT1L (08h, 01h)
Channel 1 Conversion Result Register (8-Bit Register)
Initialization
This register is cleared to 00h on all forms of reset.
Read/Write Access
This register is read only.
CRSLT1L.0–OVR1
CH1 Overrange Flag. The overrange flag is set to 1 by hardware if the current conversion causes
overranging of the C–to–D conversion. This bit is cleared to 0 if the current conversion does not cause
overranging.
CRSLT1L[3:1]
Reserved. Read returns 0.
CRSLT1L[7:4]
Channel 1 Conversion Result Bits [3:0]. This register contains the lower 4 bits of the C–to–D conversion.
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