參數(shù)資料
型號: MAX1101CWG
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: 模擬信號調(diào)理
英文描述: Single-Chip, 8-Bit CCD Digitizer with Clamp and 6-Bit PGA
中文描述: SPECIALTY ANALOG CIRCUIT, PDSO24
封裝: 0.300 INCH, MS-013AD, SOIC-24
文件頁數(shù): 9/12頁
文件大?。?/td> 110K
代理商: MAX1101CWG
M
S ingle-Chip, 8-Bit CCD Digitizer
with Clamp and 6-Bit PGA
_______________________________________________________________________________________
9
Input/Output T ransfer Func tion
CCD Input
Figure 11 shows the MAX1101 transfer function for
CCDIN. Coding is binary, with a -4LSB offset added to
ensure that offsets within the MAX1101, which can be
positive or negative, do not cause the ADC to be out of
range. Full-scale input range at CCDIN is:
(V
REF+
- V
REF-
) / G
PGA
where G
PGA
is the gain of the programmable gain
amplifier.
Analog Inputs (AIN_)
The transfer function for auxiliary inputs is shown in
Figure 11. Again, coding is binary and full-scale range
is V
REF-
to V
REF+
. An offset has not been added to
these channels; however, code transitions occur at the
1/2LSB point, as shown in Figure 12.
Implementing Correlated
Double S ampling (CDS ) or
Blac k-Level Compensation
The CLAMP circuit in the MAX1101 can be used to either
accomplish CDS or to compensate for the CCD black
level. To accomplish CDS, CLAMP is activated once per
CCD (OUT)
VIDSAMP
CLAMP
DATA
SCLK
SHIFT REG
ADC REG
ADC
PGA
D6 D5 D4 D3
DATA N-3
DATA N-2
DATA N-2
DATA N-1
DATA N
DATA N+1
DATA N-1
DATA N
LSB N-1
MSB N-1
LSB N
MSB N
LSB N+1
MSB N+1
LSB N+2
MSB N+2
AUTO-ZERO
SAMPLE N
VIDEON
VIDEON+1
VIDEON+2
VIDEON+3
SAMPLE N
SAMPLE N+1
SAMPLE N+2
SAMPLE N+3
SAMPLE N+1
SAMPLE N+2
SAMPLE N+3
AUTO-ZERO
AUTO-ZERO
AUTO-ZERO
D2 D1 D0
D7
D6 D5 D4 D3 D2 D1 D0
D7
D6 D5 D4 D3 D2 D1 D0
D7
D6 D5 D4 D3 D2 D1 D0
D7
D7
DATA N-3
DATA N-2
DATA N-1
DATA N
Figure 9. MODE = 1 Timing Showing Data Latency
BLACK CELL
BLACK CELL
VIDEO N
CCD (OUT)
VIDSAMP
CLAMP
(ONCE PER LINE)
CLAMP
(ONCE PER CELL)
Figure 10. MODE = 1 Timing Showing Relationship of CLAMP to VIDSAMP
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