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參數(shù)資料
| 型號： | MAX1101CWG |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | 模擬信號調(diào)理 |
| 英文描述： | Single-Chip, 8-Bit CCD Digitizer with Clamp and 6-Bit PGA |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, PDSO24 |
| 封裝： | 0.300 INCH, MS-013AD, SOIC-24 |
| 文件頁數(shù)： | 10/12頁 |
| 文件大小： | 110K |
| 代理商： | MAX1101CWG |
M
S ingle-Chip, 8-Bit CCD Digitizer
with Clamp and 6-Bit PGA
10
______________________________________________________________________________________
pixel during the CCD output waveform’s reset phase. To
compensate for the CCD black level, CLAMP is activated
during the black-pixel portion of the linear array, as
shown in Figure 10. Each of these modes requires a dif-
ferent value of C
EXT
, as described in the following sec-
tion.
Choosing C
EXT
for CDS
In CDS applications, C
EXT
= 4nF. This value is the best
compromise to minimize errors due to the CLAMP switch
resistance/C
EXT
time constant and switch charge injec-
tion. The following equation represents the error due to
incomplete charging of C
EXT
during integration time:
ε
=
V
RESET
x e
-t/RC
where
V
RESET
= the maximum change in reset level
from one pixel to the next, t = CLAMP pulse width, and
R = CLAMP switch resistance (150
max). At a sample
rate of 670kHz, with t = 750nsec, a 4nF capacitor
removes at least 70% of the change in reset voltage
level. Typically, R = 60
, which corresponds to a 96%
cancellation of the change in reset level.
The offset due to switch charge injection is represented
by 13pC / 4nF = 3mV. Note that this error will behave
like any DC offset; that is, it will be constant from pixel
to pixel.
Choosing C
EXT
in Black-Level Compensation
In activating CLAMP once per line to compensate for the
CCD black level, the recommended value of C
EXT
is
governed by the following equations:
C
EXT
≥
12nF
and
C
EXT
≤
N x t x 760pF/μsec
where N is the number of light-shielded cells, and t is
the width of the CLAMP pulse in μsec.
The second equation ensures that the time constant
formed by R x C
EXT
is small enough that the black level
is captured to within 0.5mV during the dark pixel
phase. For example, in an array with 27 dark pixels at a
670kHz sample rate, with t = 750nsec, the second
equation becomes C
EXT
≤
15nF. Capacitors smaller
than 12nF can be used; however, offset increases due
to switch charge injection, as explained in the section
Choosing C
EXT
for CDS.
11. . .111
DIGITAL
OUTPUT
11. . .110
11. . .101
100. . .000
00. . .111
00. . .110
00. . .101
00. . .100
00. . .011
00. . .010
00. . .001
00. . .000
249
FS
251
FS
124
FS
23
FS
-3
256
V
VIDEO
= VOLTAGE DIFFERENCE BETWEEN THE
VIDEOLEVEL AND THE PRE-CHARGE (RESET) LEVEL.
V
FS
-4
FS
21
FS
-1
FS
22
FS
-2
FS
250
FS
PGA
V
FS
=V
REF+
- V
REF-
V
VIDEO
Figure 11. Transfer Function for CCDIN
Figure 12. Transfer Function for AIN
111. . . . 111
DIGITAL
OUTPUT
111. . . . 110
111. . . . 101
100. . . 000
000. . . 011
000. . . 010
000. . . 001
000. . . 000
V
REF-
253
FS
255
FS
23
FS
21
FS
22
FS
24
FS
254
FS
V
FS
= V
REF+
- V
REF-
V
AIN_
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