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參數(shù)資料
| 型號： | MAX1101CWG |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | 模擬信號調理 |
| 英文描述： | Single-Chip, 8-Bit CCD Digitizer with Clamp and 6-Bit PGA |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, PDSO24 |
| 封裝： | 0.300 INCH, MS-013AD, SOIC-24 |
| 文件頁數(shù)： | 8/12頁 |
| 文件大?。?/td> | 110K |
| 代理商： | MAX1101CWG |
M
S ingle-Chip, 8-Bit CCD Digitizer
with Clamp and 6-Bit PGA
8
_______________________________________________________________________________________
LOAD controls the loading of data into the internal stor-
age registers during data input. Once all eight input bits
have been clocked into the shift register, a rising edge on
LOAD clocks the data into the appropriate storage regis-
ter (mux or PGA), decoded from the first two input bits.
The logic is divided into four blocks: the two storage reg-
isters, the serial I/O port, and a power-on reset genera-
tor. The registers are reset by the power-on reset to
place them in a predictable state (input channel = CCD,
PGA gain = -2) on power-up. The power-on reset typical-
ly has a 2.1μs pulse width.
The serial I/O port consists of a shift register, an 8-bit
storage register, decode logic to clock input data into
the appropriate storage register, and an output driver.
The 8-bit storage register takes input data from the
ADC.
Input Buffers and Output Drivers
The DATA driver is capable of driving 50pF load capaci-
tance while meeting the output delay specifications
given in the Electrical Characteristics. The gates of the P-
channel and N-channel drivers are driven separately. If
MODE is low, both drivers are off and the output is high
impedance.
The VIDSAMP, CLAMP, SCLK, and LOAD inputs are
buffered and have hysteresis to reject noise with slow-
slewing signal edges.
__________Applic ations Information
MAX 1101 T iming
Figure 7 shows the timing configuration when MODE =
0 and data is loaded into the MAX1101. Figure 8 shows
timing when MODE = 1 and the CCD signal is digitized.
Figure 9 is an expansion of Figure 8, illustrating the
two-VIDSAMP-cycle data latency. Figure 10 shows the
relationship of CLAMP to VIDSAMP when MODE = 1.
MODE
SCLK
LOAD
t
MSU
t
SPW
t
SPW
t
SL
t
LD
t
LS
t
DSU
A0
A1
D5
D4
D3
D2
D1
D0
t
DH
DATA
Figure 7. MODE = 0 Timing
CCD OUT
VIDSAMP
D6
D5
D7
CLAMP
SCLK
DATA
D4
D3
D2
D1
D0
RESET FEEDTHROUGH
PRECHARGE LEVEL
VIDEOLEVEL
t
CPW
t
VB
t
BS
t
VS
t
RB
t
BC
t
VB
t
VLS
t
VLD
t
SD
DATA OUTPUT AFTER D0 IS UNSPECIFIED
t
Q
t
VR
Figure 8. MODE = 1 Timing
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MAX1101CWG+ | 制造商:Maxim Integrated Products 功能描述:CCD DIGITIZER 24SOIC W - Rail/Tube |
| MAX1101CWG+T | 制造商:Maxim Integrated Products 功能描述:CCD DIGITIZER 24SOIC W - Tape and Reel |
| MAX1101CWG-T | 功能描述:模數(shù)轉換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| MAX1102 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:8-Bit CODECs |
| MAX11020ATL+ | 功能描述:模數(shù)轉換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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