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參數(shù)資料
| 型號： | MAX1101CWG |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | 模擬信號調(diào)理 |
| 英文描述： | Single-Chip, 8-Bit CCD Digitizer with Clamp and 6-Bit PGA |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, PDSO24 |
| 封裝： | 0.300 INCH, MS-013AD, SOIC-24 |
| 文件頁數(shù)： | 7/12頁 |
| 文件大?。?/td> | 110K |
| 代理商： | MAX1101CWG |
M
S ingle-Chip, 8-Bit CCD Digitizer
with Clamp and 6-Bit PGA
_______________________________________________________________________________________
7
MODE
MODE controls the direction of data transfer. When
MODE = 0, data is being shifted into the MAX1101 at
the DATA pin either for the mux or the PGA. When
MODE = 1, the ADC output is shifted out from the
MAX1101 at the DATA pin. Data is shifted in and out of
the MAX1101 at the rising edge of SCLK.
LOAD
LOAD is normally low and used only when MODE = 0.
Once all eight bits have been clocked in, bring LOAD
high to update the MAX1101 registers.
DATA
DATA is a bidirectional I/O pin. MODE controls the
direction of data transfer. When MODE = 1, DATA is
configured as an output from the shift register. Data is
clocked out of the shift register by SCLK’s rising edge.
When MODE = 0, DATA is configured as an input to the
shift register, shifted in by the rising edge of SCLK. In
this mode, the DATA output driver is disabled, putting
DATA into a high-impedance state and allowing it to be
driven externally.
Data Output
Data is clocked in and out of the device with the rising
edge of SCLK. The first bit (the MSB, D7) immediately
follows the falling edge of VIDSAMP (Figures 7 and 8).
The first rising edge of SCLK clocks out the next bit,
D6. Data is loaded into the shift register at the falling
edge of VIDSAMP. Following the output of D0, DATA
output is unspecified for additional SCLK pulses.
Eight-bit-wide storage and output registers hold data
from the ADC and delay the data output. The timing dia-
gram in Figure 9 shows the data latency of two
VIDSAMP cycles. New data is available after the second
falling edge of VIDSAMP.
Data Input
During data input, the first two bits (A0, A1) are the
address, selecting either the mux or PGA. The next six
bits set the input channel or PGA gain (Table 1).
CLAMP and VIDSAMP
The last two digital inputs are VIDSAMP and CLAMP.
VIDSAMP controls the overall cycle timing, with one
VIDSAMP cycle corresponding to one CCD pixel. The
input is sampled into the ADC by the falling edge of
VIDSAMP. CLAMP controls the black sample switch,
which sets a reference DC voltage level (V
REF+
) at the
capacitively coupled CCDIN input. The sample switch
is on when CLAMP is high.
Control and Interface Logic
The control and interface logic consists of a serial I/O
port, which shifts data into and out of the MAX1101, and
two registers for storing the mux channel and the PGA
gain data.
Table 1. Control-Byte Format
REFBIAS
REF+
REF-
REFGND
200
1k
800
Figure 6. Reference Resistor String
X = Don’t Care
1
1
1
1
1
1
1
0
Set PGA Gain to -9.875
0
1
1
1
1
1
1
0
Set PGA Gain to -9.750
1
0
0
0
0
0
1
0
Set PGA Gain to -2.125
0
0
0
0
0
0
1
0
Set PGA Gain to -2
X
X
X
0
0
1
0
0
Select AIN2
X
X
X
0
1
0
0
0
Select AIN1
X
X
X
0
0
0
0
0
Select CCD input
X
X
X
X
X
X
X
1
No Operation
—
—
—
—
—
—
1
0
Address CCD PGA
—
—
—
—
—
—
0
0
Address Analog Input Mux
D0
LSB
D1
D2
D3
D4
D5
MSB
A1
A0
FUNCTION
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