參數(shù)資料
型號(hào)： MAX108
廠商： Maxim Integrated Products, Inc.
元件分類： 運(yùn)動(dòng)控制電子
英文描述： 【5V, 1.5Gsps, 8-Bit ADC with On-Chip 2.2GHz Track/Hold Amplifier
中文描述： ±5V、1.5Gsps、8位、超高速、ADC，帶有片上2.2GHz采樣/保持放大器
文件頁(yè)數(shù)： 20/32頁(yè)
文件大?。?/td> 428K
代理商： MAX108
M
AC-Coupling Clock Inputs
The clock inputs CLK+ and CLK- can be driven with
PECL logic if the clock inputs are AC-coupled. Under
this condition, connect CLKCOM to GNDI. Single-
ended ECL/PECL/sine-wave drive is also possible if the
undriven clock input is reverse-terminated to GNDI
through a 50
resistor in series with a capacitor whose
value is identical to that used to couple the driven
input.
Demux Reset Operation
The MAX108 features an internal 1:2 demultiplexer that
reduces the data rate of the output digital data to one-
half the sample clock rate. Demux reset is necessary
when interleaving multiple MAX108s and/or synchroniz-
ing external demultiplexers. The simplified block dia-
gram of Figure 1 shows that the demux reset signal path
consists of four main circuit blocks. From input to out-
put, they are the reset input dual latch, the reset
pipeline, the demux clock generator, and the reset out-
put. The signals associated with the demux reset opera-
tion and the control of this section are listed in Table 6.
Reset Input Dual Latch
The reset input dual-latch circuit block accepts differ-
ential PECL reset inputs referenced to the same V
CC
O
power supply that powers the MAX108 PECL outputs.
For applications that do not require a synchronizing
reset, the reset inputs can be left open. In this case,
they will self-bias to a proper level with internal 50k
resistors and 20μA current source. This combination
creates a -1V difference between RSTIN+ and RSTIN-
to disable the internal reset circuitry. When driven with
PECL logic levels terminated with 50
to (V
CC
O - 2V),
the internal biasing network can easily be overdriven.
Figure 14 shows a simplified schematic of the reset
input structure.
To properly latch the reset input data, the setup time
(t
SU
) and the data-hold time (t
HD
) must be met with
respect to the rising edge of the sample clock. The tim-
ing diagram of Figure 15 shows the timing relationship
of the reset input and sampling clock.
±5V, 1.5Gsps, 8-Bit ADC with
On-Chip 2.2GHz Track/Hold Amplifier
20
______________________________________________________________________________________
Table 5. DC-Coupled Clock Drive Options
-2V
Differential ECL
Figure 13d
ECL
Drive
ECL Drive
-2V
Single-Ended ECL
Figure 13c
-1.3V
ECL Drive
GNDI
Differential Sine Wave
Figure 13b
-10dBm to +4dBm
-10dBm to +4dBm
CLK-
External 50
to GNDI
REFERENCE
CLOCK DRIVE
CLKCOM
GNDI
CLK+
Single-Ended Sine Wave
Figure 13a
-10dBm to +4dBm
50k
50k
RSTIN+
RSTIN-
RESET INPUTS ARE
ESD PROTECTED
(NOT SHOWN IN THIS
SIMPLIFIED DRAWING).
20
μ
A
GNDD
V
CC
O
Figure 14. Simplified Reset Input Structure
RSTIN+
50%
50%
CLK+
CLK-
RSTIN-
50%
t
SU
t
HD
Figure 15. Reset Input Timing Definitions
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