參數(shù)資料
型號(hào)： MAX108
廠(chǎng)商： Maxim Integrated Products, Inc.
元件分類(lèi)： 運(yùn)動(dòng)控制電子
英文描述： 【5V, 1.5Gsps, 8-Bit ADC with On-Chip 2.2GHz Track/Hold Amplifier
中文描述： ±5V、1.5Gsps、8位、超高速、ADC，帶有片上2.2GHz采樣/保持放大器
文件頁(yè)數(shù)： 14/32頁(yè)
文件大?。?/td> 428K
代理商： MAX108
M
REFOUT to REFIN. This connects the reference output
to the positive input of the reference buffer. The buffer’s
negative input is internally connected to GNDR. GNDR
must be connected to GNDI on the user’s application
board. If required, REFOUT can source up to 2.5mA to
supply external devices.
An adjustable external reference can be used to adjust
the ADC’s full-scale range. To use an external refer-
ence supply, connect a high-precision reference to the
REFIN pin and leave the REFOUT pin floating. In this
configuration, REFOUT
must not
be simultaneously
connected, to avoid conflicts between the two refer-
ences. REFIN has a typical input resistance of 5k
and
accepts input voltages of +2.5V ±200mV. For best per-
formance, Maxim recommends using the MAX108’s
internal reference.
Digital Outputs
The MAX108 provides data in offset binary format to
differential PECL outputs. A simplified circuit schematic
of the PECL output cell is shown in Figure 5. All PECL
outputs are powered from V
CC
O, which may be operat-
ed from any voltage between +3.0V to V
CC
D for flexible
interfacing with either +3.3V or +5V systems. The nomi-
nal V
CC
O supply voltage is +3.3V.
All PECL outputs on the MAX108 are open-emitter
types and must be terminated at the far end of each
transmission line with 50
to V
CC
O - 2V. Table 1 lists all
MAX108 PECL outputs and their functions.
Demultiplexer Operation
The MAX108 features an internal demultiplexer that
provides for three different modes of operation (see the
following sections on Demultiplexed DIV2 Mode, Non-
Demultiplexed DIV1 Mode, and Decimation DIV4
Mode) controlled by two TTL/CMOS-compatible inputs:
DEMUXEN and DIVSELECT.
DEMUXEN enables or disables operation of the internal
1:2 demultiplexer. A logic high on DEMUXEN activates
the internal demultiplexer, and a logic low deactivates
it. With the internal demultiplexer enabled, DIVSELECT
controls the selection of the operational mode. DIVSE-
LECT low selects demultiplexed DIV2 mode, and DIV-
SELECT high selects decimation DIV4 mode (Table 2).
±5V, 1.5Gsps, 8-Bit ADC with
On-Chip 2.2GHz Track/Hold Amplifier
14
______________________________________________________________________________________
DIFF.
PAIR
500
500
1.8mA
GNDD
GNDD
GNDD
V
CC
O
A_+/P_+
A_-/P_-
Figure 5. Simplified PECL Output Structure
Table 1. PECL Output Functions
FUNCTIONAL DESCRIPTION
P0+ to P7+, P0- to P7-
Primary-Port Differential Outputs from LSB to MSB. A “+” indicates the true outputs; a “-”
denotes the complementary outputs.
PECL OUTPUT SIGNALS
RSTOUT+, RSTOUT-
Reset Output True and Complementary Outputs
DREADY+, DREADY-
Data-Ready Clock True and Complementary Outputs. These signal lines are used to latch
the output data from the primary to the auxiliary output ports. Data changes on the rising
edge of the DREADY clock.
OR+, OR-
Overrange True and Complementary Outputs
A0+ to A7+, A0- to A7-
Auxiliary-Port Differential Outputs from LSB to MSB. A “+” indicates the true outputs; a “-”
denotes the complementary outputs.
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