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參數(shù)資料
| 型號： | MAX108 |
| 廠商： | Maxim Integrated Products, Inc. |
| 元件分類： | 運(yùn)動控制電子 |
| 英文描述： | 【5V, 1.5Gsps, 8-Bit ADC with On-Chip 2.2GHz Track/Hold Amplifier |
| 中文描述： | ±5V、1.5Gsps、8位、超高速、ADC，帶有片上2.2GHz采樣/保持放大器 |
| 文件頁數(shù)： | 16/32頁 |
| 文件大小： | 428K |
| 代理商： | MAX108 |
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M
Decimation DIV4 Mode
The MAX108 also offers a special decimated, demulti-
plexed output (Figure 8) that discards every other input
sample and outputs data at one-quarter the input sam-
pling rate for system debugging at slower output data
rates. With an input clock of 1.5GHz, the effective output
data rate will be reduced to 375MHz per output port in
the DIV4 mode (Table 2). Since every other sample is
discarded, the effective sampling rate is 750Msps.
Overrange Operation
A single differential PECL overrange output bit (OR+,
OR-) is provided for both primary and auxiliary demulti-
plexed outputs. The operation of the overrange bit
depends on the status of the internal demultiplexer. In
demultiplexed DIV2 mode and decimation DIV4 mode,
the OR bit will flag an overrange condition if either the
primary or auxiliary port contains an overranged sam-
ple (Table 2). In non-demultiplexed DIV1 mode, the OR
port will flag an overrange condition only when the pri-
mary output port contains an overranged sample.
Applications Information
Single-Ended Analog Inputs
The MAX108 T/H amplifier is designed to work at full
speed for both single-ended and differential analog
inputs (Figure 9). Inputs VIN+ and VIN- feature on-chip,
laser-trimmed 50
termination resistors to provide
excellent voltage standing-wave ratio (VSWR) perfor-
mance.
±5V, 1.5Gsps, 8-Bit ADC with
On-Chip 2.2GHz Track/Hold Amplifier
16
______________________________________________________________________________________
Table 2. Demultiplexer Operation
NOTE:
THE LATENCY TO THE PRIMARY PORT REMAINS 7.5 CLOCK CYCLES, WHILE THE LATENCY OF THE AUXILIARY PORT INCREASES TO 9.5 CLOCK CYCLES.
THIS EFFECTIVELY DISCARDS EVERY OTHER SAMPLE AND REDUCES THE OUTPUT DATA RATE TO 1/4 THE SAMPLE CLOCK RATE.
CLK-
CLK+
n
n+1
n+2
n+3
n+4
n+5
n-2
n+2
n+6
n+7
n+8
n+9
n+10
n+11
n+12
n+13
ADC SAMPLE NUMBER
ADC SAMPLES ON THE RISING EDGE OF CLK+
CLK
DREADY
AUXILIARY
DATA PORT
PRIMARY
DATA PORT
DREADY+
DREADY-
n
n+4
Figure 8. Decimation DIV4-Mode Timing Diagram
X = Don’t care
DIV4
375Msps/port
High
Flags overrange data appearing in either
the primary or auxiliary port.
High
DEMUX MODE
DIV2
750Msps/port
DIV1
750Msps (max)
DIVSELECT
Low
X
OVERRANGE BIT OPERATION
DEMUXEN
High
Low
Flags overrange data appearing in primary
port only.
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