參數(shù)資料
型號(hào): MAX106CHC
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: ADC
英文描述: 【5V, 600Msps, 8-Bit ADC with On-Chip 2.2GHz Bandwidth Track/Hold Amplifier
中文描述: 1-CH 8-BIT FLASH METHOD ADC, PARALLEL ACCESS, PBGA192
封裝: 25 X 25 MM, ESBGA-192
文件頁(yè)數(shù): 6/32頁(yè)
文件大?。?/td> 758K
代理商: MAX106CHC
M
±5V, 600Msps, 8-Bit ADC with On-Chip
2.2GHz Bandwidth Track/Hold Amplifier
6
_______________________________________________________________________________________
Typical Operating Characteristics
(V
CC
A = V
CC
I = V
CC
D = +5.0V, V
EE
= -5.0V, V
CC
O = +3.3V, REFIN connected to REFOUT, f
S
= 600Msps, T
A
= +25°C, unless other-
wise noted.)
8.00
10
100
1000
EFFECTIVE NUMBER OF BITS vs.
ANALOG INPUT FREQUENCY
(SINGLE-ENDED ANALOG INPUT DRIVE)
M
ANALOG INPUT FREQUENCY (MHz)
E
6.75
6.50
7.25
7.50
7.00
7.75
-6dBFS
-1dBFS
-12dBFS
8.00
10
100
1000
EFFECTIVE NUMBER OF BITS vs.
ANALOG INPUT FREQUENCY
(DIFFERENTIAL ANALOG INPUT DRIVE)
M
ANALOG INPUT FREQUENCY (MHz)
E
6.75
6.50
7.25
7.50
7.00
7.75
-6dBFS
-1dBFS
-12dBFS
50
10
100
1000
SIGNAL-TO-NOISE PLUS DISTORTION
vs. ANALOG INPUT FREQUENCY
(SINGLE-ENDED ANALOG INPUT DRIVE)
M
ANALOG INPUT FREQUENCY (MHz)
S
47
48
46
49
-1dBFS
-12dBFS
-6dBFS
50
10
100
1000
SIGNAL-TO-NOISE PLUS DISTORTION
vs. ANALOG INPUT FREQUENCY
(DIFFERENTIAL ANALOG INPUT DRIVE)
M
ANALOG INPUT FREQUENCY (MHz)
S
47
48
46
49
-1dBFS
-12dBFS
-6dBFS
50
10
100
1000
SIGNAL-TO-NOISE RATIO vs.
ANALOG INPUT FREQUENCY
(SINGLE-ENDED ANALOG INPUT DRIVE)
M
ANALOG INPUT FREQUENCY (MHz)
S
30
38
42
34
46
-1dBFS
-12dBFS
-6dBFS
50
10
100
1000
SIGNAL-TO-NOISE RATIO vs.
ANALOG INPUT FREQUENCY
(DIFFERENTIAL ANALOG INPUT DRIVE)
M
ANALOG INPUT FREQUENCY (MHz)
S
30
38
42
34
46
-6dBFS
-1dBFS
-12dBFS
Note 12:
Total harmonic distortion (THD) is computed from the first five harmonics.
Note 13:
Guaranteed by design with a reset pulse width of one clock period or longer.
Note 14:
The DREADY to DATA propagation delay is measured from the 50% point on the rising edge of the DREADY signal (when
the output data changes) to the 50% point on a data output bit. This places the falling edge of the DREADY signal in the
middle of the data output valid window, within the differences between the DREADY and DATA rise and fall times, which
gives maximum setup and hold time for latching external data latches.
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