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參數(shù)資料
| 型號(hào)： | MAX106CHC |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | ADC |
| 英文描述： | 【5V, 600Msps, 8-Bit ADC with On-Chip 2.2GHz Bandwidth Track/Hold Amplifier |
| 中文描述： | 1-CH 8-BIT FLASH METHOD ADC, PARALLEL ACCESS, PBGA192 |
| 封裝： | 25 X 25 MM, ESBGA-192 |
| 文件頁數(shù)： | 18/32頁 |
| 文件大?。?/td> | 758K |
| 代理商： | MAX106CHC |
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M
±5V, 600Msps, 8-Bit ADC with On-Chip
2.2GHz Bandwidth Track/Hold Amplifier
18
______________________________________________________________________________________
Offset Adjust
The MAX106 provides an analog input (VOSADJ) to com-
pensate for system offsets. The offset adjust input is a
self-biased voltage divider from the internal +2.5V preci-
sion reference. The nominal open-circuit voltage is one-
half the reference voltage. With an input resistance of
typically 25k
, this pin may be driven by an external
10k
potentiometer (Figure 11) connected between
REFOUT and GNDI to correct for offset errors. This con-
trol provides a typical ±5.5LSB offset adjustment range.
Clock Operation
The MAX106 clock inputs are designed for either sin-
gle-ended or differential operation (Figure 12) with flexi-
ble input drive requirements. Each clock input is
terminated with an on-chip, laser-trimmed 50
resistor
to CLKCOM (clock-termination return). The CLKCOM
termination voltage can be connected anywhere
between ground and -2V for compatibility with standard
ECL drive levels.
The clock inputs are internally buffered with a preampli-
fier to ensure proper operation of the data converter,
even with small-amplitude sine-wave sources. The
MAX106 was designed for single-ended, low-phase-
noise sine-wave clock signals with as little as 100mV
amplitude (-10dBm). This eliminates the need for an
external ECL clock buffer and its added jitter.
Single-Ended Clock Inputs (Sine-Wave Drive)
Excellent performance is obtained by AC- or DC-cou-
pling a low-phase-noise sine-wave source into a single
clock input (Figure 13a, Table 5). For proper DC bal-
ance, the undriven clock input should be externally
50
reverse-terminated to GNDI.
Table 4. Ideal Input Voltage and Output Code Results for Differential Operation
-125mV
-125mV + 0.5LSB
11111111 (full scale)
+125mV
VIN-
1
11111111
+125mV - 0.5LSB
0
OVERRANGE BIT
0V
+125mV - 0.5LSB
01111111
toggles
10000000
0V
0
00000001
-125mV + 0.5LSB
0
+125mV
00000000 (zero scale)
-125mV
0
VIN+
OUTPUT CODE
GNDI
10k
POT
REFOUT
VOSADJ
MAX106
Figure 11. Offset Adjust with External 10k
Potentiometer
CLK+
CLK INPUTS ARE
ESD PROTECTED
(NOT SHOWN IN THIS
SIMPLIFIED DRAWING).
CLKCOM
CLK-
50
+0.8V
50
GNDI
V
EE
Figure 12. Simplified Clock Input Structure (Single-Ended/
Differential)
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