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參數(shù)資料
| 型號： | MAX104CHC |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | ADC |
| 英文描述： | 【5V, 1Gsps, 8-Bit ADC with On-Chip 2.2GHz Track/Hold Amplifier |
| 中文描述： | 1-CH 8-BIT FLASH METHOD ADC, PARALLEL ACCESS, PBGA192 |
| 封裝： | 25 X 25 MM, ESBGA-192 |
| 文件頁數(shù)： | 14/32頁 |
| 文件大?。?/td> | 637K |
| 代理商： | MAX104CHC |
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M
REFOUT to REFIN. This connects the reference output
to the positive input of the reference buffer. The buffer’s
negative input is internally connected to GNDR. GNDR
must be connected to GNDI on the user’s application
board. REFOUT can source up to 2.5mA to supply
external devices if required.
An adjustable external reference can be used to adjust
the ADC’s full-scale range. To use an external refer-
ence supply, simply connect a high-precision reference
to the REFIN pin and leave the REFOUT pin floating. In
this configuration, REFOUT
must not
be simultaneously
connected to avoid conflicts between the two refer-
ences. REFIN has a typical input resistance of 5k
and
accepts input voltages of +2.5V ±200mV. Using the
MAX104’s internal reference is recommended for best
performance.
Digital Outputs
The MAX104 provides data in offset binary format to dif-
ferential PECL outputs. A simplified circuit schematic of
the PECL output cell is shown in Figure 5. All PECL out-
puts are powered from V
CC
O, which may be operated
from any voltage between +3.0V to V
CC
D for flexible
interfacing with either +3.3V or +5V systems. The nomi-
nal V
CC
O supply voltage is +3.3V.
All PECL outputs on the MAX104 are open-emitter
types and must be terminated at the far end of each
transmission line with 50
to V
CC
O - 2V. Table 1 lists all
MAX104 PECL outputs and their functions.
Demultiplexer Operation
The MAX104 features an internal data demultiplexer
that provides for three different modes of operation (see
the following sections on Demultiplexed DIV2 Mode,
Non-Demultiplexed DIV1 Mode, and Decimation DIV4
Mode) controlled by two TTL/CMOS-compatible inputs:
DEMUXEN and DIVSELECT.
DEMUXEN enables or disables operation of the internal
1:2 demultiplexer. A logic high on DEMUXEN activates
the internal demultiplexer, and a logic low deactivates
it. With the internal demultiplexer enabled, DIVSELECT
controls the selection of the operational mode. DIVSE-
LECT low selects demultiplexed DIV2 mode, and DIV-
SELECT high selects decimation DIV4 mode (Table 2).
±5V, 1Gsps, 8-Bit ADC with
On-Chip 2.2GHz Trac k/Hold Amplifier
14
______________________________________________________________________________________
Auxiliary-Port Differential Outputs from LSB to MSB. A “+” indicates the true outputs; a “-”
denotes the complementary outputs.
A0+, A0-, A1+, A1-, A2+, A2-,
A3+, A3-, A4+, A4-, A5+, A5-,
A6+, A6-, A7+, A7-
Overrange True and Complementary Outputs
Reset Output True and Complementary Outputs
OR+, OR-
Data-Ready Clock True and Complementary Outputs. These signal lines are used to latch
the output data from the primary to the auxiliary output ports. Data changes on the rising
edge of the DREADY clock.
DREADY+, DREADY-
RSTOUT+, RSTOUT-
PECL OUTPUT SIGNALS
Primary-Port Differential Outputs from LSB to MSB. A “+” indicates the true outputs; a “-”
denotes the complementary outputs.
P0+, P0-, P1+, P1-, P2+, P2-,
P3+, P3-, P4+, P4-, P5+, P5-,
P6+, P6-, P7+, P7-
FUNCTIONAL DESCRIPTION
DIFF.
PAIR
500
500
1.8mA
GNDD
GNDD
GNDD
V
CC
O
A_+/P_+
A_-/P_-
Figure 5. Simplified PECL Output Structure
Table 1. PECL Output Functions
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