參數(shù)資料
型號: MAX104CHC
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: ADC
英文描述: 【5V, 1Gsps, 8-Bit ADC with On-Chip 2.2GHz Track/Hold Amplifier
中文描述: 1-CH 8-BIT FLASH METHOD ADC, PARALLEL ACCESS, PBGA192
封裝: 25 X 25 MM, ESBGA-192
文件頁數(shù): 12/32頁
文件大小: 637K
代理商: MAX104CHC
M
±5V, 1Gsps, 8-Bit ADC with
On-Chip 2.2GHz Trac k/Hold Amplifier
12
______________________________________________________________________________________
_______________Detailed Desc ription
The MAX104 is an 8-bit, 1Gsps flash analog-to-digital
converter (ADC) with on-chip track/hold (T/H) amplifier
and differential PECL-compatible outputs. The ADC
(Figure 1) employs a fully differential 8-bit quantizer
and a unique encoding scheme to limit metastable
states to typically one error per 10
16
clock cycles, with
no error exceeding 1LSB max.
An integrated 8:16 output demultiplexer simplifies inter-
facing to the part by reducing the output data rate to
one-half the sampling clock rate. This demultiplexer
has internal reset capability that allows multiple
MAX104s to be time-interleaved to achieve higher
effective sampling rates.
When clocked at 1Gsps, the MAX104 provides a typi-
cal effective number of bits (ENOB) of >7.5 bits at an
analog input frequency of 500MHz. The analog input of
the MAX104 is designed for differential or single-ended
use with a ±250mV full-scale input range. In addition,
this ADC features an on-chip +2.5V precision bandgap
reference. If desired, an external reference can also be
used.
CLK-
RSTIN+
RSTIN-
VOSADJ
BANDGAP
REFERENCE
+2.5V
CLK+
CLKCOM
VIN-
VIN+
REF
OUT
REF
IN
DEMUXEN DIVSELECT
DEMUX
CLOCK
DRIVER
16
50
50
50
50
RSTOUT
A0–A7
P0–P7
DREADY
OR
DIFFERENTIAL
PECL OUTPUTS
T/H
CLOCK
DRIVER
ADC
CLOCK
DRIVER
REFERENCE
AMPLIFIER
2
2
DEMUX
CLOCK
GENERATOR
RESET INPUT
DUAL LATCH
RESET
PIPELINE
GNDI
GNDI
GNDR
DELAYED
RESET
16
16
2
2
T/H AMPLIFIER
LOGIC
CLOCK
DRIVER
BIAS CURRENTS
OVERRANGE
BIT
AUXILIARY
DATA PORT
PRIMARY
DATA PORT
DATA
READY CLOCK
DEMUX
RESET OUTPUT
8-BIT
FLASH ADC
MAX104
Figure 1. Simplified Functional Diagram
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