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參數資料
| 型號： | MAX1035EUP+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數： | 7/31頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 14BIT SER 115KSPS 20TSSOP |
| 產品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 2,500 |
| 位數： | 14 |
| 采樣率（每秒）： | 115k |
| 數據接口： | MICROWIRE?，串行，SPI? |
| 轉換器數目： | 1 |
| 功率耗散（最大）： | 879mW |
| 電壓電源： | 模擬和數字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-TSSOP（0.173"，4.40mm 寬） |
| 供應商設備封裝： | 20-TSSOP |
| 包裝： | 帶卷 (TR) |
| 輸入數目和類型： | 4 個單端，單極；4 個單端，雙極；2 個差分，單極；2 個差分，雙極 |
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Analog Input Circuitry
The analog inputs can be individually configured for
either differential or single-ended conversions by writing
the associated analog input configuration byte (Table 2).
The analog input signal source must be capable of dri-
ving the ADC’s 6k
input resistance (Figure 6).
Figure 6 shows the simplified analog input circuit. The
analog inputs are ±6V fault tolerant and are protected
by back-to-back diodes. The summing junction voltage,
VSJ, is a function of the channel’s input common-mode
voltage:
As a result, the analog input impedance is relatively
constant over the input voltage as shown in Figure 5.
Single-ended conversions are internally referenced to
AGND1 (Tables 3 and 4). In differential mode, IN+ and
IN- are selected according to Tables 3 and 5. When con-
figuring differential channels, the differential pair follows
the analog configuration byte for the positive channel.
For example, to configure CH2 and CH3 for a ±VREF dif-
ferential conversion, set the CH2 analog configuration
byte for a differential conversion with the ±VREF range
(1010 1100). To initiate a conversion for the CH2 and
CH3 differential pair, issue the command 1010 0000.
Analog Input Bandwidth
The MAX1034/MAX1035 input-tracking circuitry has a
1.5MHz small-signal bandwidth. The 1.5MHz input
bandwidth makes it possible to digitize high-speed
transient events. Harmonic distortion increases when
digitizing signal frequencies above 15kHz as shown in
the -SFDR, THD vs. Analog Input Frequency plot in the
Typical Operating Characteristics.
Analog Input Range and Fault Tolerance
Figure 7 illustrates the software-selectable single-
ended analog input voltage range that produces a valid
digital output. Each analog input channel can be inde-
pendently programmed to one of seven single-ended
input ranges by setting the R[2:0] control bits with
DIF/SGL = 0.
V
R
RR
V
R
RR
V
SJ
CM
.
=
+
×+
+
×
1
12
2 375
1
12
MAX1034/MAX1035
8-/4-Channel, ±VREF Multirange Inputs,
Serial 14-Bit ADCs
______________________________________________________________________________________
15
CS
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
DIN
S
C2
C1
C0
0
ANALOG INPUT
TRACK AND HOLD*
DOUT
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
X
BYTE 1
BYTE 2
BYTE 3
BYTE 4
SSTRB
HOLD
TRACK
HOLD
HIGH
IMPEDANCE
tACQ
*TRACK AND HOLD TIMING IS CONTROLLED BY SCLK.
fSAMPLE
≈ fSCLK / 32
SAMPLING INSTANT
HIGH
IMPEDANCE
Figure 2. External Clock-Mode Conversion (Mode 0)
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