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參數(shù)資料
| 型號： | MAX1035EUP+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 17/31頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 14BIT SER 115KSPS 20TSSOP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 2,500 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 115k |
| 數(shù)據(jù)接口： | MICROWIRE?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 879mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-TSSOP |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 4 個單端，單極；4 個單端，雙極；2 個差分，單極；2 個差分，雙極 |
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MAX1034/MAX1035
8-/4-Channel, ±VREF Multirange Inputs,
Serial 14-Bit ADCs
24
______________________________________________________________________________________
M2
M1
M0
MODE
0
External Clock (DEFAULT)
0
1
External Acquisition
0
1
0
Internal Clock
0
1
Reserved
1
0
Reset
1
0
1
Reserved
1
0
Partial Power-Down
1
Full Power-Down
Table 8. Mode-Control Bits M[2:0]
For the external acquisition mode, CS must remain low
for the first 15 clock cycles and then rise on or after the
falling edge of the 16th clock cycle as shown in Figure 3.
For optimal performance, idle DIN and SCLK during the
conversion. With careful board layout, transitions at DIN
and SCLK during the conversion have a minimal impact
on the conversion result.
After the conversion is complete, SSTRB asserts high
and CS can be brought low to read the conversion
result. SSTRB returns low on the rising SCLK edge of
the subsequent start bit.
Internal Clock Mode (Mode 2)
In internal clock mode, the internal clock controls both
acquisition and conversion of the analog signal. The inter-
nal clock starts approximately 100ns to 400ns after the
falling edge of the eighth SCLK and has a rate of about
4.5MHz. The analog input sampling instant occurs at the
falling edge of the 11th internal clock signal (Figure 4).
For the internal clock mode, CS must remain low for the
first seven SCLK cycles and then rise on or after the
falling edge of the eighth SCLK cycle. After the conver-
sion is complete, SSTRB asserts high and CS can be
brought low to read the conversion result. SSTRB returns
low on the rising SCLK edge of the subsequent start bit.
Reset (Mode 4)
As shown in Table 8, set M[2:0] = 100 to reset the
MAX1034/MAX1035 to its default conditions. The
default conditions are full power operation with each
channel configured for ±VREF, bipolar, single-ended
conversions using external clock mode (mode 0).
Partial Power-Down Mode (Mode 6)
As shown in Table 8, when M[2:0] = 110, the device
enters partial power-down mode. In partial power-
down, all analog portions of the device are powered
down except for the reference voltage generator and
bias supplies.
To exit partial power-down, change the mode by issu-
ing one of the following mode-control bytes (see the
Mode Control section):
External-Clock-Mode Control Byte
External-Acquisition-Mode Control Byte
Internal-Clock-Mode Control Byte
Reset Byte
Full Power-Down-Mode Control Byte
This prevents the MAX1034/MAX1035 from inadvertent-
ly exiting partial power-down mode because of a CS
glitch in a noisy digital environment.
Full Power-Down Mode (Mode 7)
When M[2:0] = 111, the device enters full power-down
mode and the total supply current falls to 1A (typ). In
full power-down, all analog portions of the device are
powered down. When using the internal reference,
upon exiting full power-down mode, allow 10ms for the
internal reference voltage to stabilize prior to initiating a
conversion.
To exit full power-down, change the mode by issuing
one of the following mode-control bytes (see the
Mode
Control section):
External-Clock-Mode Control Byte
External-Acquisition-Mode Control Byte
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