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參數(shù)資料
| 型號： | MAX1035EUP+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 4/31頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 14BIT SER 115KSPS 20TSSOP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 115k |
| 數(shù)據(jù)接口： | MICROWIRE?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 879mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-TSSOP |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 4 個單端，單極；4 個單端，雙極；2 個差分，單極；2 個差分，雙極 |
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MAX1034/MAX1035
8-/4-Channel, ±VREF Multirange Inputs,
Serial 14-Bit ADCs
12
______________________________________________________________________________________
Pin Description
PIN
MAX1034
MAX1035
NAME
FUNCTION
1
2
AVDD1
Analog Supply Voltage 1. Connect AVDD1 to a +4.75V to +5.25V power-supply voltage.
Bypass AVDD1 to AGND1 with a 0.1F capacitor.
2
3
CH0
Analog Input Channel 0
3
4
CH1
Analog Input Channel 1
4
5
CH2
Analog Input Channel 2
5
6
CH3
Analog Input Channel 3
6
—
CH4
Analog Input Channel 4
7
—
CH5
Analog Input Channel 5
8
—
CH6
Analog Input Channel 6
9
—
CH7
Analog Input Channel 7
10
7
CS
Active-Low Chip-Select Input. When CS is low, data is clocked into the device from DIN on
the rising edge of SCLK. With CS low, data is clocked out of DOUT on the falling edge of
SCLK. When CS is high, activity on SCLK and DIN is ignored and DOUT is high impedance.
11
8
DIN
Serial Data Input. When CS is low, data is clocked in on the rising edge of SCLK. When CS is
high, transitions on DIN are ignored.
12
9
SSTRB
Serial-Strobe Output. When using the internal clock, SSTRB rising edge transitions indicate
that data is ready to be read from the device. When operating in external clock mode, SSTRB
is always low. SSTRB does not tri-state, regardless of the state of CS, and therefore requires
a dedicated I/O line.
13
10
SCLK
Serial Clock Input. When CS is low, transitions on SCLK clock data into DIN and out of DOUT.
When CS is high, transitions on SCLK are ignored.
14
11
DOUT
Serial Data Output. When CS is low, data is clocked out of DOUT with each falling SCLK
transition. When CS is high, DOUT is high impedance.
15
12
DGNDO
Digital I/O Ground. DGND, DGNDO, AGND3, AGND2, and AGND1 must be connected together.
16
13
DGND
Digital Ground. DGND, DGNDO, AGND3, AGND2, and AGND1 must be connected together.
17
14
DVDDO
Digital I/O Supply Voltage Input. Connect DVDDO to a +2.7V to +5.25V power-supply voltage.
Bypass DVDDO to DGNDO with a 0.1F capacitor.
18
15
DVDD
Digital-Supply Voltage Input. Connect DVDD to a +4.75V to +5.25V power-supply voltage.
Bypass DVDD to DGND with a 0.1F capacitor.
19
16
REFCAP
Bandgap-Voltage Bypass Node. For external reference operation, connect REFCAP to AVDD
or internal reference operation, bypass REFCAP with a 0.01F capacitor to AGND1 (VREFCAP
≈ 4.096V).
20
17
REF
Reference-Buffer Output/ADC Reference Input. For external reference operation, apply an
external reference voltage from 3.800V to 4.136V to REF. For internal reference operation,
bypassing REF with a 1F capacitor to AGND1 sets VREF = 4.096V ±1%.
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