參數(shù)資料
型號(hào): M8803F3Y-90K1T
廠商: STMICROELECTRONICS
元件分類: 微控制器/微處理器
英文描述: 1M X 1 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQCC52
封裝: PLASTIC, LCC-52
文件頁(yè)數(shù): 51/85頁(yè)
文件大?。?/td> 601K
代理商: M8803F3Y-90K1T
55/85
M88 FAMILY
Table 41. Example of M88x3Fxx FLASH+PSD Typical Power Calculation at VCC = 5.0 V AC/DC
Condit ions
Highest Composite PLD input frequency
(Freq PLD)
= 8 MHz
MCU ALE frequency (Freq ALE)
= 4 MHz
% Flash Access
= 80%
% SRAM access
= 15%
% I/O access
= 5% (no additional power above base)
Operational Modes
% Normal
= 10%
% Power Down Mode
= 90%
Number of product terms used
(from fitter report)
= 45 PT
% of total product terms
= 45/182 = 24.7%
Turbo Mode
= ON
Calculation (using typical values)
ICC total
= Ipwrdown x %pwrdown + %normal x (ICC (ac) + ICC (dc))
= Ipwrdown x %pwrdown + % normal x (%flash x 2.5 mA/MHz x Freq ALE
+ %SRAM x 1.5 mA/MHz x Freq ALE
+ % PLD x 2 mA/MHz x Freq PLD
+ #PT x 400
A/PT)
=50
A x 0.90 + 0.1 x (0.8 x 2.5 mA/MHz x 4 MHz
+ 0.15 x 1.5 mA/MHz x 4 MHz
+2 mA/MHz x 8 MHz
+ 45 x 0.4 mA/PT)
=45
A + 0.1 x (8 + 0.9 + 16 + 18 mA)
=45
A + 0.1 x 42.9
=45
A + 4.29 mA
= 4.34 mA
This is the operating power with no EEPROM writes or Flash erases. Calculation is based on IOUT =0 mA.
progress, and also when data is being written to
EEPROM.
TSTAT and TERR can be configured as open-
drain type signals during an “ISC_ENABLE”
command. This facilitates a wired-OR connection
of TSTAT signals from several M88 Family
devices and a wired-OR connection of TERR
signals from those same devices. This is useful
when several M88 Family devices are “chained”
together in a JTAG environment.
Security and Flash Memories and EEPROM
Protection
When the security bit is set, the device cannot be
read on a device programmer or through the JTAG
Port. When using the JTAG Port, only a full chip
erase command is allowed.
All other program/erase/verify commands are
blocked. Full chip erase returns the part to a non-
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