- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄45053 > M8803F3Y-90K1T (STMICROELECTRONICS) 1M X 1 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQCC52 PDF資料下載
參數(shù)資料
| 型號(hào)： | M8803F3Y-90K1T |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 1M X 1 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQCC52 |
| 封裝： | PLASTIC, LCC-52 |
| 文件頁數(shù)： | 41/85頁 |
| 文件大小： | 601K |
| 代理商： | M8803F3Y-90K1T |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁當(dāng)前第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁
M88 FAMILY
46/85
Figu re 31. Port D Structure
INTERNAL
DATA
BUS
DATA OUT
REG.
DQ
WR
ECS [ 2:0]
READ MUX
P
D
B
CPLD- INPUT
DIR REG.
DATA IN
ENABLE PRODUCT
TERM (.OE)
OUTPUT
SELECT
OUTPUT
MUX
PORT D PIN
DATA OUT
AI02889
t Peripheral Mode – Port A only
Port C – Functionality and Structure
Port C can be configured to perform one or more
of the following functions (see Figure 31):
t MCU I/O Mode
t CPLD Output – McellBC[7:0] outputs can be
connected to Port B or Port C.
t CPLD Input – via the Input Macrocells
t Address In – Additional high address inputs
using the Input Macrocells.
t In-System Programming – JTAG port can be
enabled for programming/erase of the M88x3Fxx
FLASH+PSD device. (See the section entitled
“Programming
In-Circuit
using
the
JTAG
Interface”, on page 53, for more information on
JTAG programming.)
t Open Drain – Port C pins can be configured in
Open Drain Mode
t Battery Backup features – PC2 can be
configured as a Battery Input (VSTBY) pin.
PC4 can be configured as a Battery On Indicator
output pin, indicating when VCC is less than VBAT.
Port C does not support Address Out mode, and
therefore no Control Register is required.
Pin PC7 may be configured as the DBE input in
certain microcontroller interfaces.
Port D – Functionality and Structure
Port D has three I/O pins. See Figure 32. This port
does not
support Address
Out
mode,
and
therefore no Control Register is required. Port D
can be configured to perform one or more of the
following functions:
t MCU I/O Mode
t CPLD Output – (external chip select)
t CPLD Input – direct input to CPLD, no Input
Macrocells
t Slew rate – pins can be set up for fast slew rate
Port D pins can be configured in PSDsoft as input
pins for other dedicated functions:
t PD0 – ALE, as address strobe input
t PD1 – CLKIN, as clock input to the Macrocells
Flip Flops and APD counter
t PD2 – CSI, as active low chip select input. A
high input will disable the Flash/EEPROM/SRAM
and CSIOP.
External Chip Select
The CPLD also provides three chip select outputs
on Port D pins that can be used to select external
devices. Each chip select (ECS0-2) consists of
one product term that can be configured active
high or low. The output enable of the pin is
controlled by either the output enable product term
or the Direction Register. (See Figure 32.)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M8813F3Y-90K1T | 1M X 1 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQCC52 |
| M906-01-125.0000LF | 125 MHz, OTHER CLOCK GENERATOR, CQCC36 |
| M906-01-125.0000LF | 125 MHz, OTHER CLOCK GENERATOR, CQCC36 |
| M906-01-187.5000LF | 187.5 MHz, OTHER CLOCK GENERATOR, CQCC36 |
| M906-01I156.2500 | 156.25 MHz, OTHER CLOCK GENERATOR, CQCC36 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M8805/100-007 | 制造商:OTTO Engineering Inc 功能描述:M8805/100-007 |
| M8805/100-009 | 制造商:OTTO Engineering Inc 功能描述:M8805/100-009 |
| M8805/100-010 | 制造商:OTTO Engineering Inc 功能描述:M8805/100-010 |
| M8805/100-015 | 制造商:OTTO Engineering Inc 功能描述:M8805/100-015 |
| M8805/100-016 | 制造商:OTTO Engineering Inc 功能描述:M8805/100-016 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。