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參數(shù)資料
| 型號： | M7536 |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | 8-Bit Single-Chip Microcomputer(8位單片微控制器) |
| 中文描述： | 8位單片機（8位單片微控制器） |
| 文件頁數(shù)： | 125/225頁 |
| 文件大小： | 1672K |
| 代理商： | M7536 |
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2-58
APPLICATION
2.4 USB
7532/7536 Group User’s Manual
Fig. 2.4.7 Register structures relevant to USB (1)
TB
RB
RxRDY SUME BSTFE
0
0
PIDE
0
CRCE FEOPE
0
EOP
0
TxRDY
1
EOP detection flag
0: Not detected
1: Detect
False EOP error flag
0: No error
1: False EOP error
CRC error flag
0: No error
1: CRC error
Setting condition of this flag to “1” is as follows;
PID of DATA0 or DATA1 cannot be detected at data phase after OUT or SETUP
token
ACK PID cannot be received at handshake phase during IN transaction.
This bit is cleared to “0” by writing dummy to this register.
Bit stuffing error flag
0: No error
1: Bit stuffing error
This bit is set to “1” when bit stuffing error occurs at data phase or handshake phase.
This bit is cleared to “0” by writing dummy to this register.
Summing error flag
0: No error
1: Summing error
This bit is set to “1” when any error of FEOPE, CRCE, PIDE, or BSTFE occurs.
This bit is cleared to “0” by writing dummy to this register.
Receive buffer full
flag
1: Buffer full
This bit is set to “1” when data is transferred from shift register to buffer by hardware.
This bit is cleared to “0” by reading from buffer.
Set/
Clear
Ena-
ble
0
Transmit buffer register (TB) [Address 18
16
]
CPU
RD
CPU
WR
Set/
Clear
H/W
RD
Use
H/W
WR
CPU
RD
Ena-
ble
CPU
WR
H/W
RD
H/W
WR
Set/
Clear
CPU
RD
Ena-
ble
CPU
WR
H/W
RD
H/W
WR
Set/
Clear
b7
b6
b5
b4
b3
b2
b1
b0
b7
b6
b5
b4
b3
b2
b1
b0
b7
b6
b5
b4
b3
b2
b1
b0
Initial value
Receive buffer register (RB) [Address 18
16
]
0
0
0
0
0
0
0
Initial value
0
0
Initial value
USB status register (USBSTS) [Address 19
16
]
Ena-
ble
Ena-
ble
Ena-
ble
Ena-
ble
Ena-
ble
Ena-
ble
Set
Set
Set
Set
Set
Set
Clear
Clear
Clear
Clear
Clear
Clear
–
After setting data to address 0018
16
,
the data is transferred to the transmit
shift register automatically.
Receive buffer register can be read out
by reading data from address 0018
16
.
Transmit buffer empty flag (TxRDY) is cleared by writing data to this register.
Receive buffer full flag (RxRDY) is cleared by reading this register.
Transmit buffer
empty flag
This bit is set to “1” when data is transferred from buffer to shift register by hardware.
This bit is cleared to “0” by writing to buffer.
0: Buffer full
1: Buffer empty
PID error flag
0: No error
1: PID error
0: Buffer empty
Setting condition of this flag to “1” is as follows;
Normal EOP detected by hardware
False EOP flag (FEOPE) set
Time is out with EOP not detected at data phase or handshake phase
This bit is cleared to “0” by writing dummy to this register.
This bit is set to “1” when the phase is not completed normally.
This bit is cleared to “0” by writing dummy to this register.
This bit is set to “1” when the CRC error occurs at the same timing of EOP detection
flag.
This bit is to “0” cleared by writing dummy to this register.
–
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