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參數(shù)資料
| 型號(hào)： | M59MR032C |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 32 Mbit 2Mb x16, Mux I/O, Dual Bank, Burst 1.8V Supply Flash Memory |
| 中文描述： | 32兆位的2Mb x16插槽，復(fù)用的I / O，雙行，突發(fā)1.8V電源快閃記憶體 |
| 文件頁數(shù)： | 29/49頁 |
| 文件大?。?/td> | 352K |
| 代理商： | M59MR032C |
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M59MR032C, M59MR032D
Table 29. Asynchronous Read AC Characteristics
(T
A
= –40 to 85°C; V
DD
= V
DDQ
= 1.65V to 2.0V)
Note: 1. Sampled only, not 100% tested.
2. G may be delayed by up to t
ELQV
- t
GLQV
after the falling edge of E without increasing t
ELQV
.
Symbol
Alt
Parameter
Test Condition
M59MR032
Unit
100
120
Min
Max
Min
Max
t
AVAV
t
RC
Address Valid to Next
Address Valid
E = V
IL
, G = V
IL
100
120
ns
t
AVLH
t
AVAVDH
Address valid to Latch
Enable High
G = V
IH
10
10
ns
t
AVQV
t
ACC
Address Valid to Output
Valid (Random)
E = V
IL
, G = V
IL
100
120
ns
t
AVQV1
t
PAGE
Address Valid to Output
Valid (Page)
E = V
IL
, G = V
IL
45
45
ns
t
EHQX
t
OH
Chip Enable High to Output
Transition
G = V
IL
0
0
ns
t
EHQZ
(1)
t
HZ
Chip Enable High to Output
Hi-Z
G = V
IL
20
20
ns
t
ELLH
t
ELAVDH
Chip Enable Low to Latch
Enable High
E = V
IL
, G = V
IH
10
10
ns
t
ELQV
(2)
t
CE
Chip Enable Low to Output
Valid
G = V
IL
100
120
ns
t
ELQX
(1)
t
LZ
Chip Enable Low to Output
Transition
G = V
IL
0
0
ns
t
GHQX
t
OH
Output Enable High to
Output Transition
E = V
IL
0
0
ns
t
GHQZ
(1)
t
DF
Output Enable High to
Output Hi-Z
E = V
IL
20
20
ns
t
GLQV
(2)
t
OE
Output Enable Low to
Output Valid
E = V
IL
25
35
ns
t
GLQX
(1)
t
OLZ
Output Enable Low to
Output Transition
E = V
IL
0
0
ns
t
LHAX
t
AVDHAX
Latch Enable High to
Address Transition
E = V
IL
, G = V
IH
10
10
ns
t
LHGL
Latch Enable High to
Output Enable Low
E = V
IL
10
10
ns
t
LLLH
t
AVDLAVDH
Latch Enable Pulse Width
E = V
IL
, G = V
IH
10
10
ns
t
LLQV
t
AVDLQV
Latch Enable Low to
Output Valid (Random)
E = V
IL
100
120
ns
t
LLQV1
Latch Enable Low to
Output Valid (Page)
E = V
IL
45
45
ns
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