- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄180233 > M59DR032F100N1T (NUMONYX) 2M X 16 FLASH 1.8V PROM, 100 ns, PDSO48 PDF資料下載
參數(shù)資料
| 型號： | M59DR032F100N1T |
| 廠商： | NUMONYX |
| 元件分類： | PROM |
| 英文描述： | 2M X 16 FLASH 1.8V PROM, 100 ns, PDSO48 |
| 封裝： | 12 X 20 MM, PLASTIC, TSOP-48 |
| 文件頁數(shù)： | 36/38頁 |
| 文件大小： | 270K |
| 代理商： | M59DR032F100N1T |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁當前第36頁第37頁第38頁
7/38
M59DR032A, M59DR032B
Table 8. User Bus Operations (1)
Note: 1. X = Don’t care.
Table 9. Read Electronic Signature (AS and Read CFI instructions)
Table 10. Read Block Protection (AS and Read CFI instructions)
Table 11. Read Configuration Register (AS and Read CFI instructions)
Operation
E
G
W
RP
WP
DQ15-DQ0
Write
VIL
VIH
VIL
VIH
Data Input
Output Disable
VIL
VIH
Hi-Z
Standby
VIH
XX
VIH
Hi-Z
Reset / Power Down
X
VIL
VIH
Hi-Z
Block Locking
VIL
XX
VIH
VIL
X
Code
Device
E
G
W
A0
A1
A7-A2
Other
Addresses
DQ15-DQ8
DQ7-DQ0
Manufacturer Code
VIL
VIH
VIL
0
Don’t Care
00h
20h
Device Code
M59DR032A
VIL
VIH
VIL
0
Don’t Care
00h
A0h
M59DR032B
VIL
VIH
VIL
0
Don’t Care
00h
A1h
Block Status
E
G
W
A0
A1
A20-A12
A7-A2
Other
Addresses
DQ0
DQ1
DQ15-DQ2
Protected Block
VIL
VIH
VIL
VIH
Block Address
0
Don’t Care
1
0
0000h
Unprotected Block
VIL
VIH
VIL
VIH
Block Address
0
Don’t Care
0
0000h
Locked Block
VIL
VIH
VIL
VIH
Block Address
0
Don’t Care
X
1
0000h
RP Function
E
G
W
A0
A1
A7-A2
Other Addresses
DQ10
DQ9-DQ0
DQ15-DQ11
Reset
VIL
VIH
0
Don’t Care
0
Don’t Care
Reset/Power Down
VIL
VIH
0
Don’t Care
1
Don’t Care
Automatic Standby. When in Read mode, after
150ns of bus inactivity and when CMOS levels are
driving the addresses, the chip automatically en-
ters a pseudo-standby mode where consumption
is reduced to the CMOS standby value, while out-
puts still drive the bus.
Power Down. The memory is in Power Down
when the Configuration Register is set for Power
Down and RP is at VIL. The power consumption is
reduced to the Power Down level, and Outputs are
in high impedance, independent of the Chip En-
able E, Output Enable G or Write Enable W inputs.
Block Locking. Any combination of blocks can
be temporarily protected against Program or
Erase by setting the lock register and pulling WP
to VIL (see Block Lock instruction).
Dual Bank Operations. The Dual Bank allows to
read data from one bank of memory while a pro-
gram or erase operation is in progress in the other
bank of the memory. Read and Write cycles can
be initiated for simultaneous operations in different
banks without any delay. Status Register during
Program or Erase must be monitored using an ad-
dress within the bank being modified.
Output Disable. The data outputs are high im-
pedance when the Output Enable G is at VIH with
Write Enable W at VIH.
Standby. The memory is in standby when Chip
Enable E is at VIH and the P/E.C. is idle. The pow-
er consumption is reduced to the standby level
and the outputs are high impedance, independent
of the Output Enable G or Write Enable W inputs.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M5F7924 | 24 V FIXED NEGATIVE REGULATOR, PSFM3 |
| M5F7920 | 20 V FIXED NEGATIVE REGULATOR, PSFM3 |
| M5F7918 | 18 V FIXED NEGATIVE REGULATOR, PSFM3 |
| M5F7915 | 15 V FIXED NEGATIVE REGULATOR, PSFM3 |
| M5F7910 | 10 V FIXED NEGATIVE REGULATOR, PSFM3 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M59DR032F100N6T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:32 Mbit 2Mb x16, Dual Bank, Page Low Voltage Flash Memory |
| M59DR032F100ZB1T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:32 Mbit 2Mb x16, Dual Bank, Page Low Voltage Flash Memory |
| M59DR032F100ZB6T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:32 Mbit 2Mb x16, Dual Bank, Page Low Voltage Flash Memory |
| M59DR032F120N1T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:32 Mbit 2Mb x16, Dual Bank, Page Low Voltage Flash Memory |
| M59DR032F120N6T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:32 Mbit 2Mb x16, Dual Bank, Page Low Voltage Flash Memory |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。