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參數(shù)資料
| 型號： | M39832-T15WNE6T |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | TVS BI-DIR 33V 600W DO-15 |
| 中文描述： | 單芯片8兆1兆x8或512KB的x16閃存和256千位并行EEPROM存儲器 |
| 文件頁數(shù)： | 2/36頁 |
| 文件大?。?/td> | 253K |
| 代理商： | M39832-T15WNE6T |
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Warning:
NC = Not Connected.
VSS
EF
A0
DQ8
DQ0
G
DQ1
A6
A5
A4
A1
A3
A2
EE
W
RP
NC
NC
DQ14
DQ6
DQ13
DQ5
A9
A8
A10
DQ12
DQ4
A15
A14
DQ10
DQ2
VCC
DQ11
DQ9
DQ3
A18
A17
A7
FRB
AI00845
M39832
12
13
1
24
25
36
37
48
ERB
A16
BYTE
VSS
DQ15A–1
DQ7
A13
A12
A11
Figure 2. TSOP Pin Connections
A0-A18
Address Inputs
DQ0-DQ7
Data Input/Outputs, Commands Input
DQ8-DQ14
Data Input/Outputs
DQ15A–1
Data Input/Outputs or Address Input
EE
EEPROM Array Enable
EF
Flash Array Enable
G
Output Enable
W
Write Enable
RP
Reset/Block Temporary Unprotect
ERB
EEPROM Ready/Busy Output
FRB
Flash Ready/Busy Output
BYTE
Flash Array Byte/Word Organization
V
CC
Supply Voltage
V
SS
Ground
Table 1. Signal Names
DESCRIPTION
(cont’d)
The M39832 Flash Memory array can be config-
ured as 1Mb x8 or 512Kb x16 with the BYTE input
pin. The M39832-T and M39832-B feature asymet-
rically blocked architecture providing system mem-
ory integration. Both M39832-B and M39832-T
devices have a Flash array of 19 blocks, one Boot
Block of 16 KBytes or 8 KWords, two Parameter
Blocks of 8 KBytes or 4 KWords, one Main Block
of 32 KBytes or 16 KWords and fifteen Main Blocks
of 64 KBytes or 32 KWords. The M39832-T has the
Boot Block at the top of the memory address space
and the M39832-B locates the Boot Block starting
at the bottom. The memory maps are showed in
Figures 3A and 3B. Each block can be erased
separately,any combination of blocks can be speci-
fied for multi-block erase or the entire chip may be
erased. The Erase operations are managed auto-
matically. The block erase operation can be sus-
pended in order to read from or program to any
block not being ersased, and then resumed. Block
protection provides additional data security. Each
block can be separately protected or unprotected
against Program or Erase on programming equip-
ment. All previously protected blocks can be tem-
porarily unprotected in the application. The Flash
memory array is functionally compatible with the
M29W800 Single Voltage Flash Memory device.
During a Program or Erase cycle in the Flash array
or during a Write in the EEPROM array, status bits
available on certain DQn pins provide information
on the M39832 internal logic.
PIN DESCRIPTION
Byte/Word Organization Select (BYTE)
. The
BYTE input selects the output configuration for the
Flash array: Byte-wide (x8) mode or Word-wide
(x16) mode. The EEPROM array and the 64 Bytes
OTP Row are always accessed Byte-wide (x8).
When BYTE is High, the Word-wide mode is se-
lected for the Flash array (x16) and the data are
read and programmed on DQ0-DQ15. The Flash
array is accessed with A0-A18 Adrress lines. In this
mode, data in the EEPROM array (x8) are read and
programmed on DQ0-DQ7 and the array is ac-
cessed with A0-A14. The 64 bytes OTP are read
and programmed on DQ0-DQ7 and are accessed
with A0-A5 and A6 = 0.
When BYTE is Low, the Byte-wide mode is selected
for the Flash array (x8) and the data are read and
2/36
M39832
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