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參數資料
| 型號： | M39832-T15WNE6T |
| 廠商： | 意法半導體 |
| 英文描述： | TVS BI-DIR 33V 600W DO-15 |
| 中文描述： | 單芯片8兆1兆x8或512KB的x16閃存和256千位并行EEPROM存儲器 |
| 文件頁數： | 13/36頁 |
| 文件大小： | 253K |
| 代理商： | M39832-T15WNE6T |
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Write.
A Write operation can be used for two goals:
– either write data in the EEPROM memory array
– or enter a sequence of bytes or word composing
an instruction.
The reader should note that Programming a Flash
byte or word is an instruction (see Instructions
paragraph).
Writing data requires:
– the Chip Enable (either EE or EF) to be Low
– the Write Enable (W) to be Low with Output
Enable (G) High.
Addresses in Flash array (or EEPROM array) are
latched on the falling edge of W or EF (EE) which-
ever occurs last; the data to be written in Flash
array (EEPROM array) is latched on the rising edge
of W or EF (EE) whichever occurs first.
Specific Read and Write Operations.
Device
specific data is accessed through operations de-
coding the V
ID
level applied on A9 and the logic
levels applied on address inputs (A0, A1, A6).
These specific operations are:
– Read the Manufacturer identifier
– Read the Flash identifier
– Define and Read the Flash Block protection
status
– Read the EEPROM identifier
– Write the EEPROM identifier
Note: The OTP row (64 bytes) is accessed with a
specific software sequence detailed in the para-
graph "Write in OTP row".
Instructions
An instruction is defined as a sequence of specific
Write operations. Each received byte or word is
sequentially decoded (and not executed as stand-
ard Write operations) and the instruction is exe-
cuted when the correct number of bytes or word
are properly received and the time between two
consecutive bytes or words is shorter than the
time-out value.
The sequencing of any instruction must be followed
exactly, any invalid combination of instruction bytes
or word or time-out between two consecutive bytes
or word will reset the device logic into a Read
memory state (when addressing the Flash array)
or directly decoded as a single operation when
addressing the EEPROM array.
For efficient decoding of the instruction, the two first
bytes or words of an instruction are the coded
cycles and are followed by a command confirma-
tion byte or word.
AI01698B
WRITE AAh in
Address 5555h
WRITE 55h in
Address 2AAAh
WRITE A0h in
Address 5555h
SDP is set
WRITE AAh in
Address 5555h
WRITE 55h in
Address 2AAAh
WRITE A0h in
Address 5555h
WRITE Data to
be Written in
any Address
SDP ENABLE ALGORITHM
Page
Write
Instruction
Page
Write
Instruction
WRITE
is enabled
SDP
Set
SDP
not Set
Write
in Memory
Write Data
+
SDP Set
after tWC
Figure 4. EEPROM SDP Enable Flowcharts
13/36
M39832
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