DQ
Name
Logic Level
Definition
Note
7
Data
Polling
’1’
Erase Complete or erase
block in Erase Suspend
Indicates the P/E.C. status, check during
Program or Erase, and on completion
before checking bits DQ5 for Program or
Erase Success.
’0’
Erase On-going
DQ
Program Complete or data
of non erase block during
Erase Suspend
DQ
Program On-going
6
Toggle Bit
’-1-0-1-0-1-0-1-’
Erase or Program On-going
Successive reads output complementary
data on DQ6 while Programming or Erase
operations are on-going. DQ6 remains at
constant level when P/E.C. operations are
completed or Erase Suspend is
acknowledged.
DQ
Program Complete
’-1-1-1-1-1-1-1-’
Erase Complete or Erase
Suspend on currently
addressed block
5
Error Bit
’1’
Program or Erase Error
This bit is set to ’1’ in the case of
Programming or Erase failure.
’0’
Program or Erase On-going
4
Reserved
3
Erase
Time Bit
’1’
Erase Timeout Period Expired
P/E.C. Erase operation has started. Only
possible command entry is Erase Suspend
(ES).
’0’
Erase Timeout Period
On-going
An additional block to be erased in parallel
can be entered to the P/E.C.
2
Toggle Bit
’-1-0-1-0-1-0-1-’
Chip Erase, Erase or Erase
Suspend on the currently
addressed block.
Erase Error due to the
currently addressed block
(when DQ5 = ’1’).
Indicates the erase status and allows to
identify the erased block
1
Program on-going, Erase
on-going on another block or
Erase Complete
DQ
Erase Suspend read on
non Erase Suspend block
1
Reserved
0
Reserved
Notes:
Logic level ’1’ is High, ’0’ is Low. -0-1-0-0-0-1-1-1-0- represent bit value in successive Read operations.
Table 9. Status Bit
Code
E
G
W
A0
A1
A12-A18
Other
Addresses
DQ0-DQ7
Protected Block
V
IL
V
IL
V
IH
V
IL
V
IH
Block Address
Don’t Care
01h
Unprotected Block
V
IL
V
IL
V
IH
V
IL
V
IH
Block Address
Don’t Care
00h
Table 8. Read Block Protection with AS Instruction (EF = 0, EE = 1)
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